Radiation Hardness for Silicon Oxide and Aluminum Oxide on 4H-SiC

2018 ◽  
Vol 924 ◽  
pp. 229-232 ◽  
Author(s):  
Anders Hallén ◽  
Sethu Saveda Suvanam
Keyword(s):  
Proton Irradiation ◽  
Silicon Oxide ◽  
Positive Charge ◽  
Gate Dielectric ◽  
Radiation Hardness ◽  
Flat Band ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
Radiation Hard ◽  
Mos Structures

The radiation hardness of two dielectrics, SiO2and Al2O3, deposited on low doped, n-type 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.

Defect Analysis and Reliability Characteristics of (HfZrO4)1−x(SiO2)x High-κ Dielectrics

2020 ◽  
Vol 20 (11) ◽  
pp. 6718-6722
Author(s):  
Areum Park ◽  
Pyungho Choi ◽  
Woojin Jeon ◽  
Donghyeon Lee ◽  
Donghee Choi ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Flat Band ◽  
Defect Analysis ◽  
Positive Direction ◽  
Reliability Characteristics ◽  
Capacitance Voltage ◽  
Bias Temperature Stress ◽  
Curve Shift

Hafnium zirconium silicon oxide ((HfZrO4)1−x(SiO2)x) materials were investigated through the defect analysis and reliability characterization for next generation high-κ dielectric. Silicate doped hafnium zirconium oxide (HfZrO4) films showed a reduction of negative flat-band voltage (Vfb) shift compared to pure HfZrO4. This result was caused by a decrease in donor-like interface traps (Dit) and positive border traps (Nbt). As the silicon oxide (SiO2) content increased, the Vfb was shifted in the positive direction from −1.23 to −1.10 to −0.91 V and the slope of the capacitance–voltage (C–V) curve increased. The nonparallel shift of the C–V characteristics was affected by the Dit, while the Nbt was responsible for the parallel C–V curve shift. The values of Dit reduced from 4.3 × 1011, 3.5 × 1011, and 3.0 × 1011 cm−2eV−1, as well as the values of Nbt were decreased from 5.24, 3.90 to 2.26 × 1012 cm−2. Finally, reduction of defects in the HfZrO4-base film with an addition of SiO2 affected the gate oxide reliability characteristics, such as gate leakage current (JG), bias temperature stress instability (BTSI), and time dependent gate dielectric breakdown (TDDB).

Distributions of electric parameters in MOS structures on 3C-SiC substrate

Open Physics ◽  
2013 ◽  
Vol 11 (2) ◽  
Author(s):  
Krzysztof Piskorski ◽  
Henryk Przewlocki ◽  
Romain Esteve ◽  
Mietek Bakowski
Keyword(s):  
Gate Dielectric ◽  
Contact Potential Difference ◽  
Flat Band ◽  
Electrical Parameters ◽  
Contact Potential ◽  
Mos Structure ◽  
Effective Contact ◽  
Semiconductor Voltage ◽  
Electric Parameters ◽  
Mos Structures

AbstractIn this work studies of some electrical parameters of the MOS structure based on 3C-SiC substrate are presented. The effective contact potential difference ϕMS, the barrier height at the gate-dielectric interface E BG and the flat-band in semiconductor voltage V FB were measured using several electric and photoelectric techniques. Values of these parameters obtained on structures with different gate areas decrease monotonically with increasing parameter R, defined as the ratio of the gate perimeter to the gate area. Such behavior confirmed results obtained on MOS structures on silicon substrate and also supported our hypothesis that the mechanical stress in the dielectric layer under the metal gate causes non uniform distribution of some parameters over the gate area of MOS structure.

Amorphous Silicon Based TFT and MIS Nonvolatile Memories

2007 ◽  
Vol 989 ◽  
Author(s):  
Yue Kuo ◽  
Helinda Nominanda
Keyword(s):  
Amorphous Silicon ◽  
Gate Dielectric ◽  
Low Cost ◽  
Flat Band ◽  
Nonvolatile Memories ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Voltage Hysteresis ◽  
A Charge ◽  
Silicon Based

AbstractThe amorphous silicon (a-Si:H) TFT and MIS capacitor, which include an a-Si:H layer embedded in the silicon nitride gate dielectric layer, have been prepared and characterized for memory functions. Large shifts of the threshold voltage and flat band voltage were detected in the current-voltage and capacitance-voltage hysteresis measurements. The embedded a-Si:H film functioned as a charge retention medium that stores and releases injected carriers. The devices memory capacity varied with the thickness of the embedded a-Si:H layer and the sweep voltage. These low-cost memory devices can be used in many low-temperature prepared circuits.

Capacitance-Voltage Characteristics of Metallic Gate/Oxide/a-Si:H Mos Structures

1986 ◽  
Vol 70 ◽  
Author(s):  
Ruud E. I. Schropp ◽  
Jan Snijder ◽  
Jan F. Verwey
Keyword(s):  
Density Of States ◽  
Field Effect ◽  
Low Frequency ◽  
Gate Oxide ◽  
Static Capacitance ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
Mos Structures ◽  
First Time ◽  
Effect Method

ABSTRACTThe density of states (DOS) has for the first time been calculated throughout the entire bandgap region of undoped amorphous silicon from quasi-static capacitance-voltage (QSCV) measurements using MOS structures. The QSCV DOS is compared with the DOS obtained by the field-effect method. It is shown, that the coexistence of states of a different nature at the same bandgap level can be revealed by the temperature dependence of low frequency MOS CV measurements.

Analysis of failure of C-V characteristics of MIS structure with SiO2 passivation layer deposited on InSb substrate via Raman spectroscopy

2014 ◽  
Vol 1670 ◽  
Author(s):  
Chulkyun Seok ◽  
Sujin Kim ◽  
Jaeyel Lee ◽  
Sehun Park ◽  
Yongjo Park ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Electrical Properties ◽  
Deposition Temperature ◽  
Silicon Oxide ◽  
Oxide Semiconductor ◽  
Mis Structure ◽  
Metal Insulator ◽  
Capacitance Voltage ◽  
Resonant Raman ◽  
Mos Structures

ABSTRACTThe effect of interfacial phases on the electrical properties of Au/Ti/SiO2/InSb metal-insulator (oxide)-semiconductor (MIS or MOS) structures was investigated by capacitance-voltage (C-V) measurements. With increasing the deposition temperature of silicon oxide from 100 to 350°C using PECVD, the change in the interfacial phases between SiO2 and InSb were analyzed by resonant Raman spectroscopy to verify the relation between the breakdown of C-V characteristics and the change of interfacial phases. The shape of C-V characteristics was dramatically changed when the deposition temperature was above 300°C. The C-V measurements and Raman spectra represented that elemental Sb accumulation resulted from the chemical reaction of Sb oxide with InSb substrate was responsible for the failure in the C-V characteristics of MIS structure.

scholarly journals Tailoring the Interface between Dielectric and 4H-SiC by Ion Implantation

2015 ◽  
Vol 821-823 ◽  
pp. 488-491
Author(s):  
Sethu Saveda Suvanam ◽  
David M. Martin ◽  
Carl Mikael Zetterling ◽  
Anders Hallén
Keyword(s):  
No Reduction ◽  
Oxide Semiconductor ◽  
Current Gain ◽  
Bipolar Junction Transistors ◽  
Projected Range ◽  
Fixed Charges ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
Mos Structures ◽  
Different Doses

In this paper effects of carbon (C), silicon (Si) and nitrogen (N) implantation on the interface properties of 4H-SiC/SiO2and the implications for 4H-SiC bipolar junction transistors (BJT) passivation are discussed. 4H-SiC epi-layer have been implanted with12C,14N and28Si ion at three different doses with energies of 3, 3.5 and 6 keV, respectively, resulting in a projected range of 8 nm for the three ions. Then metal oxide semiconductor (MOS) structures with SiO2as dielectric have been fabricated. Capacitance voltage measurements show an increase in the negative fixed charges for all the implanted samples as a function of implantation induced damage. Similarly, in the case of C and Si, the surface roughness increases as a function of dose and the mass of the ions. No reduction of Dits due to the implantations is seen for any of the ions. Furthermore, TCAD device simulations of npn bipolar junction transistors (BJT), using the interface and fixed charges extracted from CV measurements, show a way to further optimize current gain and breakdown properties for the BJT.

Characterization of the SiO2/SiC Interface with Impedance Spectroscopy

2009 ◽  
Vol 615-617 ◽  
pp. 501-504 ◽  
Author(s):  
Pawel A. Sobas ◽  
Ulrike Grossner ◽  
Bengt Gunnar Svensson
Keyword(s):  
Impedance Spectroscopy ◽  
Ionic Conduction ◽  
Semiconductor Interface ◽  
Transfer Processes ◽  
Capacitance Voltage ◽  
Dc Bias ◽  
The One ◽  
Cv Measurements ◽  
Mos Structures

Using impedance spectroscopy (IS) for the characterization of SiO2/4H-SiC (MOS) structures, insight on the capacitive and resistive contributions in different physical regions of the MOS structures is obtained. Changing the DC bias conditions, semiconductor, interface as well as oxide traps can be detected. The MOS capacitance, as extracted from IS data, is different from the one obtained using capacitance voltage (CV) measurements, due to the possibility of distinguishing different charge transfer processes using IS. For instance, in the investigated capacitors, a clear contribution is revealed from ionic conduction processes at bias voltages close to zero.

AlON/SiO2 Stacked Gate Dielectrics for 4H-SiC MIS Devices

2009 ◽  
Vol 615-617 ◽  
pp. 541-544 ◽  
Author(s):  
Takuji Hosoi ◽  
Makoto Harada ◽  
Yusuke Kagei ◽  
Yuu Watanabe ◽  
Takayoshi Shimura ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Gate Insulator ◽  
Flat Band ◽  
Aluminum Oxynitride ◽  
Fixed Charges ◽  
Interface Charge ◽  
Capacitance Voltage ◽  
High Dielectric ◽  
Mis Devices

We propose the use of an aluminum oxynitride (AlON) gate insulator for 4H-SiC MIS devices. Since direct deposition of AlON on 4H-SiC substrate generates a large amount of interface charge due to an interfacial reaction, a thick AlON layer was deposited on underlying thin SiO2 thermally grown in N2O ambient. To reduce the negative fixed charge density in the aluminum oxide (Al2O3) film, we used reactive sputtering of Al in an N2/O2 gas mixture. The fabricated MIS capacitor with AlON/SiO2 stacked gate dielectric shows no flat band voltage shift and negligible capacitance-voltage hysteresis (30 mV), indicating the dielectric is almost free from both fixed charges and electrical defects. Owing to the high dielectric constant of AlON (k=6.9), as compared to single N2O-SiO2 gate insulator, significant gate leakage reduction was achieved by AlON/SiO2 stacked gate dielectrics even at high-temperature, especially in a high electric field condition (>5 MV/cm).

Nanoprobe Characterization of Soft SRAM bit Fails in Advanced Technologies

2019 ◽  
Author(s):  
Satish Kodali ◽  
Chen Zhe ◽  
Chong Khiam Oh
Keyword(s):  
Yield Loss ◽  
Performance Metrics ◽  
Root Cause ◽  
Advanced Technologies ◽  
Capacitance Voltage ◽  
Defect Localization ◽  
Cv Measurements ◽  
Lightly Doped Drain ◽  
Dc Characterization

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

DESIGN, PREPRODUCTION, AND PERFORMANCE OF THE CDF RUN IIB SILICON DETECTOR

2005 ◽  
Vol 20 (16) ◽  
pp. 3811-3814
Author(s):  
◽  
PAUL LUJAN
Keyword(s):  
Building Block ◽  
Silicon Detector ◽  
Radiation Hardness ◽  
Control Signals ◽  
Lightweight Structure ◽  
And Performance ◽  
Performance Results ◽  
And Control ◽  
Radiation Hard ◽  
Detector Design

A new silicon detector was designed by the CDF collaboration for Run IIb of the Tevatron at Fermilab. The main building block of the new detector is a "supermodule" or "stave", an innovative, compact and lightweight structure of several readout hybrids and sensors with a bus cable running directly underneath the sensors to carry power, data, and control signals to and from the hybrids. The hybrids use a new, radiation-hard readout chip, the SVX4 chip. A number of SVX4 chips, readout hybrids, sensors, and supermodules were produced and tested in preproduction. The performance (including radiation-hardness) and yield of these components met or exceeded all design goals. The detector design goals, solutions, and performance results are presented.

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