980 V, 33A Normally-Off 4H-SiC Buried Gate Static Induction Transistors

2011 ◽  
Vol 679-680 ◽  
pp. 662-665 ◽  
Author(s):  
Akio Takatsuka ◽  
Yasunori Tanaka ◽  
Koji Yano ◽  
Tsutomu Yatsuo ◽  
Kazuo Arai
Keyword(s):  
Gate Voltage ◽  
High Performance ◽  
Design Parameters ◽  
Process Conditions ◽  
Avalanche Breakdown ◽  
State Characteristic ◽  
Static Induction Transistors ◽  
Static Induction ◽  
Avalanche Breakdown Voltage ◽  
Channel Region

In this work, we succeeded in developing high performance normally-off SiC buried gate static induction transistors (SiC-BGSITs). To achieve the normally-off characteristics, design parameters around the channel region were optimized and process conditions were improved to realize these parameters. The off-state characteristic of the SiC-BGSIT showed an avalanche breakdown voltage of VBR=980 V at a gate voltage of VG=0 V. Furthermore, the leakage current at VD=950 V is lower than 0.5 μA. These results indicate that the BGSIT has a good normally-off characteristic. At VG=2.5 V, an on-resistance of 28.0 mΩ corresponding to the specific on-resistance of 1.89 mΩ•cm2 was obtained and the current rating was calculated as 33 A at a power density of 200 W/cm2 in the on-state characteristic.

1270V, 1.21mΩ·cm2 SiC Buried Gate Static Induction Transistors (SiC-BGSITs)

2008 ◽  
Vol 600-603 ◽  
pp. 1071-1074 ◽  
Author(s):  
Yasunori Tanaka ◽  
Koji Yano ◽  
Mitsuo Okamoto ◽  
Akio Takatsuka ◽  
Kazuo Arai ◽  
...  
Keyword(s):  
Time Delay ◽  
The Other ◽  
Gate Electrodes ◽  
Turn On ◽  
Static Induction Transistors ◽  
Operation Temperature ◽  
Barrier Formation ◽  
Static Induction ◽  
The Difference ◽  
Channel Region

We have succeeded to fabricate SiC buried gate static induction transistors (BGSITs) with the breakdown voltage VBR of 1270 V at the gate voltage VGS of –12 V and the specific on-resistance RonS of 1.21 mΩ·cm2 at VGS = 2.5 V. The turn-off behaviors of BGSITs strongly depend on the source length WS, which is the distance between the gate electrodes. The rise time tr of BGSIT for WS = 1,070 μm is 395 nsec, while that for WS = 210 μm is 70nsec. From the 3D computer simulations, we confirmed that the difference in turn-off behavior came from the time delay in potential barrier formation in channel region because of high p+ gate resistivity. The turn-off behaviors also depend on the operation temperature, especially for long WS. On the other hand, the turn-on behaviors hardly depend on the WS and temperature.

High performance microwave static induction transistors

1983 ◽  
Author(s):  
A. Cogan ◽  
R. Regan ◽  
I. Bencuya ◽  
S. Butler ◽  
F. Rock
Keyword(s):  
High Performance ◽  
Static Induction Transistors ◽  
Static Induction

scholarly journals High‐Performance Static Induction Transistors Based on Small‐Molecule Organic Semiconductors

2020 ◽  
pp. 2000361 ◽  
Author(s):  
Erjuan Guo ◽  
Shen Xing ◽  
Felix Dollinger ◽  
Zhongbin Wu ◽  
Alexander Tahn ◽  
...  
Keyword(s):  
Organic Semiconductors ◽  
Small Molecule ◽  
High Performance ◽  
Static Induction Transistors ◽  
Static Induction

scholarly journals Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs

2021 ◽  
Author(s):  
Umar Ibrahim Minhas ◽  
Roger Woods ◽  
Georgios Karakonstantis
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
System Throughput ◽  
Design Parameters ◽  
Temporal Constraints ◽  
Shared Resources ◽  
Task Processing ◽  
High Level ◽  
Performance Computing

AbstractWhilst FPGAs have been used in cloud ecosystems, it is still extremely challenging to achieve high compute density when mapping heterogeneous multi-tasks on shared resources at runtime. This work addresses this by treating the FPGA resource as a service and employing multi-task processing at the high level, design space exploration and static off-line partitioning in order to allow more efficient mapping of heterogeneous tasks onto the FPGA. In addition, a new, comprehensive runtime functional simulator is used to evaluate the effect of various spatial and temporal constraints on both the existing and new approaches when varying system design parameters. A comprehensive suite of real high performance computing tasks was implemented on a Nallatech 385 FPGA card and show that our approach can provide on average 2.9 × and 2.3 × higher system throughput for compute and mixed intensity tasks, while 0.2 × lower for memory intensive tasks due to external memory access latency and bandwidth limitations. The work has been extended by introducing a novel scheduling scheme to enhance temporal utilization of resources when using the proposed approach. Additional results for large queues of mixed intensity tasks (compute and memory) show that the proposed partitioning and scheduling approach can provide higher than 3 × system speedup over previous schemes.

Trade-Off Analysis for the Design of a High Performance Hydrostatic Actuation System

2000 ◽  
Author(s):  
S. R. Habibi
Keyword(s):  
Mathematical Modeling ◽  
Quadratic Programming ◽  
High Performance ◽  
Design Parameters ◽  
Mathematical Functions ◽  
Trade Off ◽  
Actuation System ◽  
Trade Offs ◽  
Expected Performance ◽  
Dominant Design

Abstract This paper considers the design of a high performance hydrostatic actuation system referred to as the ElectroHydraulic Actuator (EHA). The expected performance of EHA and its dominant design parameters are identified by using mathematical modeling. The design parameters are classified into Direct and Indirect categories based on the measure of their accessibility to the designer. The Direct parameters are directly quantifiable and, can be linked to the performance of EHA through a set of mathematical functions. A prototype of EHA has been produced and described. The mathematical functions linking performance to design parameters are used to investigate design trade-offs. Design improvements to the prototype are suggested by using constrained quadratic programming.

On the Extraction of Milling Tools Out of Shrink Fit Chucks

2012 ◽  
Vol 523-524 ◽  
pp. 445-450 ◽  
Author(s):  
Berend Denkena ◽  
Dennis Heinisch
Keyword(s):  
High Performance ◽  
Experimental Investigations ◽  
Process Conditions ◽  
Geometrical Parameters ◽  
Dynamic Force ◽  
Unique Type ◽  
Milling Operations ◽  
Torque Transmission ◽  
Shrink Fit ◽  
Milling Tools

Thermal shrink fit chucks are widely used in high performance machining where excellent concentricity and high torque transmission are required. It was reported that in those milling operations, severe damage of tools, workpieces, and also machine tools occurs due to an extraction of the milling tool out of the shrink fit chuck during the process. Although, theoretically the interference fit assembly should withstand certain process forces, milling tools are apparently pulled out under special process conditions. The resulting increase of the cutting depth often leads to tool overload and breakage. So far, the phenomenon of tool extraction could not be explained. This paper presents an experimental approach of the investigation of the phenomenon of axial tool extraction. Therefore, a unique type of test rig for main spindles and tool interfaces is used. Experimental investigations on dynamic force and torque combinations leading to tool extraction are described. Results show, that the holding force is not only affected by geometrical parameters of the shrink fit chuck, but also by the applied dynamic load.

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