Characterization of Nitrided Gate Oxide Formed by RTP for SiC MOSFET Application

2011 ◽  
Vol 324 ◽  
pp. 221-224 ◽  
Author(s):  
Aurore Constant ◽  
Philippe Godignon
Keyword(s):  
Gate Oxide ◽  
Breakdown Field ◽  
Gate Oxides ◽  
Furnace Process ◽  
Surface Pretreatment ◽  
Channel Mobility ◽  
Conventional Furnace ◽  
The One

Gate oxides for SiC lateral MOSFETs have been formed in N2O by rapid thermal processing (RTP) as an alternative to the conventional furnace process. This innovative oxidation method has not only the advantage to significantly reduce the thermal budget compared to a standard oxidation, but also to produce oxide layers with quality comparable to the one grown in a conventional furnace. Moreover, a significant improvement of the oxide quality and MOSFET performance is observed when performing in-situ a H2 anneal prior to oxidation as surface pretreatment. The channel mobility and the breakdown field of the gate oxide are considerably increased.

Oxidation Process by RTP for 4H-SiC MOSFET Gate Fabrication

2011 ◽  
Vol 679-680 ◽  
pp. 500-503 ◽  
Author(s):  
Aurore Constant ◽  
Nicolas Camara ◽  
Josep Montserrat ◽  
Esther Pausas ◽  
Jean Camassel ◽  
...  
Keyword(s):  
Surface Preparation ◽  
Electrical Stability ◽  
Furnace Process ◽  
Thermal Budget ◽  
Channel Mobility ◽  
Bias Stress ◽  
Low Field ◽  
Conventional Furnace ◽  
Constant Bias

Rapid Thermal Processing (RTP) has been evaluated as an alternative to the conventional furnace process for the gate oxide formation of SiC lateral MOSFETs. We show that this innovative oxidation method has not only the advantage to significantly reduce the thermal budget compared to classical oxidation, but also produces a significant improvement of MOSFET performance when using N2O as oxidizing gas. Studying different surface preparation before gate oxidation, we demonstrate that in-situ surface preparation by H2 annealing increases considerably the channel mobility and also the electrical stability with respect to constant bias stress at low-field.

scholarly journals Electrical and Chemical Characterization of FIB-Deposited Insulators

1997 ◽  
Author(s):  
A. N. Campbell ◽  
D. M. Tanner ◽  
J. M. Soden ◽  
D. K. Stewart ◽  
A. Doyle ◽  
...  
Keyword(s):  
Focused Ion Beam ◽  
Rutherford Backscattering Spectrometry ◽  
Ion Beam ◽  
Chemical Properties ◽  
Chemical Characterization ◽  
Breakdown Field ◽  
Gate Oxides ◽  
Spectrometry Analysis ◽  
Metal Insulator Metal

Abstract The electrical and chemical properties of insulators produced by codeposition of siloxane compounds or TEOS with oxygen in a focused ion beam (FIB) system were investigated. Metal-insulator-metal capacitor structures were fabricated and tested. Specifically, leakage current and breakdown voltage were measured and used to calculate the effective resistance and breakdown field. Capacitance measurements were performed on a subset of the structures. It was found that the siloxanebased FIB-insulators had superior electrical properties to those based on TEOS. Microbeam Rutherford backscattering spectrometry analysis and Fourier transform infrared spectroscopy were used to characterize the films and to help understand the differences in electrical behavior as a function of gas chemistry and deposition conditions. Finally, a comparison is made between the results presented here, previous results for FIB-deposited insulators, and typical thermally-grown gate oxides and interlevel dielectric Si02 insulators.

scholarly journals A One-Pot Synthesis and Characterization of Antibacterial Silver Nanoparticle–Cellulose Film

Polymers ◽  
2020 ◽  
Vol 12 (2) ◽  
pp. 440 ◽  
Author(s):  
Qi-Yuan Chen ◽  
Sheng-Ling Xiao ◽  
Sheldon Q. Shi ◽  
Li-Ping Cai
Keyword(s):  
Composite Film ◽  
Food Packaging ◽  
Antibacterial Activities ◽  
Light Transmittance ◽  
Ag Nps ◽  
One Pot ◽  
One Pot Synthesis ◽  
The One

Using N,N-dimethylacetamide (DMAc) as a reducing agent in the presence of PVP-K30, the stable silver nanoparticles (Ag-NPs) solution was prepared by a convenient method for the in situ reduction of silver nitrate. The cellulose–Ag-NPs composite film (CANF) was cast in the same container using lithium chloride (LiCl) giving the Ag-NPs-PVP/DMAc solution cellulose solubility as well as γ-mercaptopropyltrimethoxysilane (MPTS) to couple Ag-NPs and cellulose. The results showed that the Ag-NPs were uniformly dispersed in solution, and the solution had strong antibacterial activities. It was found that the one-pot synthesis allowed the growth of and cross-linking with cellulose processes of Ag-NPs conducted simultaneously. Approximately 61% of Ag-NPs was successfully loaded in CANF, and Ag-NPs were uniformly dispersed in the surface and internal of the composite film. The composite film exhibited good tensile properties (tensile strength could reach up to 86.4 MPa), transparency (light transmittance exceeds 70%), thermal stability, and remarkable antibacterial activities. The sterilization effect of CANF0.04 against Staphylococcus aureus and Escherichia coli exceed 99.9%. Due to low residual LiCl/DMAc and low diffusion of Ag-NPs, the composite film may have potential for applications in food packaging and bacterial barrier.

Evaluation Of 2.0 nm Grown and Deposited Dielectrics in 0.1 μm PMOSFETs

1998 ◽  
Vol 525 ◽  
Author(s):  
A. Srivastava ◽  
H. H. Heinisch ◽  
E. Vogel ◽  
C. Parker ◽  
C. M. Osburn ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Deposition Process ◽  
Gate Oxides ◽  
Boron Doped ◽  
Excellent Control ◽  
Lower Temperature ◽  
Boron Penetration

ABSTRACTThe quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.

Electrical Properties of High-K LaLuO3 Gate Oxide for SOI MOSFETs

2011 ◽  
Vol 276 ◽  
pp. 87-93
Author(s):  
Y.Y. Gomeniuk ◽  
Y.V. Gomeniuk ◽  
A. Nazarov ◽  
P.K. Hurley ◽  
Karim Cherkaoui ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Interface State ◽  
Channel Length ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Threshold Voltages

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

TXRF Characterization of Trace Metal Contamination in Thin Gate Oxides

1992 ◽  
Vol 259 ◽  
Author(s):  
R. S. Hockett ◽  
Diane Hymes
Keyword(s):  
Metal Contamination ◽  
Gate Oxide ◽  
Silicon Substrates ◽  
Qualitative Information ◽  
Gate Oxides ◽  
Quantitative Estimates ◽  
Oxide Reliability ◽  
First Time ◽  
Non Destructive

ABSTRACTMetal contamination on the surface of silicon substrates before gate oxidation is known to affect gate oxide reliability. For the first time this study presents a non-destructive, analytical measurement of transition metals in an 8nm gate oxide grown by a 920 °C-10min-dry oxidation of an intentionally contaminated silicon surface. The TECHNOS TREX 610 TXRF anglescan of the gate oxide provides qualitative information on the location of the metals. The data indicate the Fe is on or in the oxide, the Cu is below the oxide, the Zn is on the oxide, and the Ni may be both in the oxide and below the oxide layer. In addition, quantitative estimates from the TXRF data indicate that all the original Fe and Cu are present, while only portions of Zn and Ni are detected after the oxidation.

Synthesis and Characterization of Nanoscale CeO2 Catalyst for deNOx

2005 ◽  
Vol 23 ◽  
pp. 95-98 ◽  
Author(s):  
S. Kawi ◽  
Y.P. Tang ◽  
K. Hidajat ◽  
L.E. Yu
Keyword(s):  
Water Vapor ◽  
Catalytic Reduction ◽  
Precipitation Method ◽  
Synthesis And Characterization ◽  
In Situ Xrd ◽  
Surface Areas ◽  
Rich Condition ◽  
The One

Hydrothermal and precipitation methods have been applied to synthesize nanoscale CeO2 catalysts for selective catalytic reduction of NO with hydrocarbon under oxygen-rich condition. The former procedure has the advantage of enhancing the hydrothermal stability of nanomaterial. BET results show that their surface areas are about 30-80 m2/g. Based on TEM results, hydrothermally prepared CeO2 shows very uniform grain shaped particles with size around 10-20 nanometers. Its thermal stability up to 1200°C has been confirmed by in-situ XRD. Furthermore, deNOx reaction with propene as reducing agent in the presence of 5% oxygen has been carried out to compare catalysts prepared by the above two methods. Results show that hydrothermally prepared catalyst is more active than the one prepared by precipitation method. The latter one lost half of its activity in the presence of 5% water vapor, while the former one could stand up to 10% water vapor in the gas mixture without losing much activity.

Implementation of Sub-Resolvable Features for Precise Electrical Characterization of SiC Gate Oxide Parameters

2012 ◽  
Vol 717-720 ◽  
pp. 797-800
Author(s):  
J. Jay McMahon ◽  
Liang Chun Yu ◽  
Jody Fronheiser ◽  
J.T. Elson ◽  
Roger Kovalec ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Screening Tests ◽  
Compensation Mechanism ◽  
Gate Oxides ◽  
Attractive Option ◽  
Van Der Pauw ◽  
Similar Yield

We describe fabrication of Van der Pauw (VDP) structures for characterization of gate oxides grown on 4H SiC epi surfaces. Implementation of sub-resolvable features (SRF) as a corner compensation mechanism is analyzed with challenges and advantages presented. Results of on-wafer screening tests suggest that implementation of SRFs widens tolerance for misalignment, producing similar yield between uncompensated VDPs with 0.2 micron overlap and compensated VDPs with 0.1 micron overlap for structures with best alignment. Optimization of SRFs for SiC could be an attractive option for extending lithographic capability in advanced devices.

Inversion-Channel MOS Devices for Characterization of 4H-SiC/SiO2 Interfaces

2015 ◽  
Vol 821-823 ◽  
pp. 480-483 ◽  
Author(s):  
A.I. Mikhaylov ◽  
Alexey V. Afanasyev ◽  
V.V. Luchinin ◽  
S.A. Reshanov ◽  
Adolf Schöner ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Gate Oxide ◽  
Process Optimisation ◽  
Gate Oxides ◽  
Mos Structure ◽  
Mos Devices ◽  
Inversion Channel ◽  
And Inversion ◽  
Thermally Grown

Electrical properties of the gate oxides thermally grown in N2O on n-type and p-type 4H-SiC have been compared using conventional MOS structure and inversion-channel MOS structure, respectively. Sufficient difference in the electrical properties of the gate oxides grown on n-type and p-type 4H-SiC was revealed. We conclude that the gate oxide process optimisation using inversion-channel MOS devices is superior as compared to the conventional MOS structure.

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