Measurement Issues Affecting Threshold-Voltage Instability Characterization of SiC MOSFETs

2016 ◽  
Vol 858 ◽  
pp. 461-464 ◽  
Author(s):  
Ronald Green ◽  
Aivars J. Lelis ◽  
Daniel B. Habersat

This work focuses on measurement issues that affect the accuracy of positive bias temperature instability measurements of SiC power MOSFETs using a conventional sweep technique to characterize the threshold voltage, VT. Threshold-voltage shifts occurring during stress are readily recoverable during the measurement, resulting in an underestimation in VT degradation. Recovery of VT due to gate-stress relaxation before or during the measurement was a major source of measurement error that was mitigated by performing an immediate sweep down in gate voltage, VGS, from the stress bias toward threshold. Allowing the gate bias to drop to zero just prior to measuring by sweeping VGS positively resulted in smaller observed degradation due to VT recovery. This result is important, especially in cases where the gate stress has to be completely removed before making any electrical measurements. The VT shift caused by bias stress can quickly recover and yield test results that underestimate the effect of the applied stress. A full recovery of VT was observed following a positive gate bias stress for conditions where the gate was either subject to a negative gate voltage for a few seconds, or when VGS was maintained at zero volts for several minutes.

2017 ◽  
Vol 897 ◽  
pp. 549-552 ◽  
Author(s):  
Mitsuo Okamoto ◽  
Mitsuru Sometani ◽  
Shinsuke Harada ◽  
Hiroshi Yano ◽  
Hajime Okumura

The threshold voltage (Vth) instability of 4H-SiC MOSFETs was investigated using high-speed IV measurement instrument. DC stress measurement of wide time span ranging from 10-6 to 103 s without relaxation effect was conducted. The high-speed measurement allowed of dynamic ΔVth measurement under pulsed AC gate bias stress. We investigated effects of NO POA in gate oxidation process on the Vth instabilities.


2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000275-000280 ◽  
Author(s):  
R. J. Kaplar ◽  
D. R. Hughart ◽  
S. Atcitty ◽  
J. D. Flicker ◽  
S. DasGupta ◽  
...  

Commercially available, 1200 V SiC power MOSFETs have been characterized under bias-temperature stress conditions. Two generations of devices from a single manufacturer were tested. For the first-generation MOSFETs, both plastic- and metal-packaged devices were evaluated, whereas for the second-generation MOSFETs, only plastic-packaged devices were tested. Threshold voltage was observed to decrease with increasing temperature in the absence of gate bias stress, as expected. Drain leakage current increased with increasing temperature above the rated temperature of 125°C for first-generation plastic-packaged parts, with the leakage ~10× higher for the plastic-packaged parts compared to the metal-packaged parts. A negative gate voltage was shown to reduce drain leakage current for the metal-packaged parts only, suggesting a parasitic leakage path associated with the plastic packaging. The threshold voltage shift ΔVT was minimal for T < 125°C. ΔVT increased with increasing temperature above 125°C, and was larger for negative gate voltage bias stress, suggesting that the oxide is more sensitive to trapping of holes than trapping of electrons. ΔVT was insensitive to the type of package. The second-generation SiC MOSFET showed significantly less susceptibility to bias temperature stress, especially for negative gate voltage, indicating improvement in device design and/or processing in the second-generation MOSFET. Switching gate stress showed complex behavior, with a rapid initial shift in VT followed by a much slower shift. Initial testing indicates a strong dependence on duty cycle and possible influence of self-heating. More detailed study of reliability under switching conditions is needed.


2019 ◽  
Vol 954 ◽  
pp. 133-138
Author(s):  
Ao Liu ◽  
Song Bai ◽  
Run Hua Huang ◽  
Tong Tong Yang ◽  
Hao Liu

The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.


2015 ◽  
Vol 54 (4) ◽  
pp. 044101 ◽  
Author(s):  
Fei Sang ◽  
Maojun Wang ◽  
Chuan Zhang ◽  
Ming Tao ◽  
Bing Xie ◽  
...  

2019 ◽  
Vol 963 ◽  
pp. 749-752
Author(s):  
Jose Ortiz Gonzalez ◽  
Olayiwola Alatise ◽  
Philip A. Mawby

The material properties of SiC make SiC power devices a superior alternative to the conventional Si power devices. However, the reliability of the gate oxide has been a major concern, limiting the adoption of SiC power MOSFETs as the power semiconductor of choice in applications which demand a high reliability. The threshold voltage (VTH) shift caused by Bias Temperature Instability (BTI) has focused the attention of different researchers, with multiple publications on this topic. This paper presents a novel method for evaluating the threshold voltage shift due to negative gate bias and its recovery when the gate bias stress is removed. This method could enable gate oxide reliability assessment techniques and contribute to new qualification methods.


1990 ◽  
Vol 11 (5) ◽  
pp. 203-205 ◽  
Author(s):  
Y. Tang ◽  
D.M. Kim ◽  
Y.-H. Lee ◽  
B. Sabi

2020 ◽  
Vol 1004 ◽  
pp. 554-558
Author(s):  
Kwangwon Lee ◽  
Young Ho Seo ◽  
Taeseop Lee ◽  
Kyeong Seok Park ◽  
Martin Domeij ◽  
...  

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.


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