scholarly journals Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs at High Temperatures

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000275-000280 ◽  
Author(s):  
R. J. Kaplar ◽  
D. R. Hughart ◽  
S. Atcitty ◽  
J. D. Flicker ◽  
S. DasGupta ◽  
...  
Keyword(s):  
Leakage Current ◽  
Threshold Voltage ◽  
Gate Voltage ◽  
First Generation ◽  
Second Generation ◽  
Power Mosfets ◽  
Bias Stress ◽  
Bias Temperature Stress ◽  
Increasing Temperature ◽  
Negative Gate Voltage

Commercially available, 1200 V SiC power MOSFETs have been characterized under bias-temperature stress conditions. Two generations of devices from a single manufacturer were tested. For the first-generation MOSFETs, both plastic- and metal-packaged devices were evaluated, whereas for the second-generation MOSFETs, only plastic-packaged devices were tested. Threshold voltage was observed to decrease with increasing temperature in the absence of gate bias stress, as expected. Drain leakage current increased with increasing temperature above the rated temperature of 125°C for first-generation plastic-packaged parts, with the leakage ~10× higher for the plastic-packaged parts compared to the metal-packaged parts. A negative gate voltage was shown to reduce drain leakage current for the metal-packaged parts only, suggesting a parasitic leakage path associated with the plastic packaging. The threshold voltage shift ΔVT was minimal for T < 125°C. ΔVT increased with increasing temperature above 125°C, and was larger for negative gate voltage bias stress, suggesting that the oxide is more sensitive to trapping of holes than trapping of electrons. ΔVT was insensitive to the type of package. The second-generation SiC MOSFET showed significantly less susceptibility to bias temperature stress, especially for negative gate voltage, indicating improvement in device design and/or processing in the second-generation MOSFET. Switching gate stress showed complex behavior, with a rapid initial shift in VT followed by a much slower shift. Initial testing indicates a strong dependence on duty cycle and possible influence of self-heating. More detailed study of reliability under switching conditions is needed.

Measurement Issues Affecting Threshold-Voltage Instability Characterization of SiC MOSFETs

2016 ◽  
Vol 858 ◽  
pp. 461-464 ◽  
Author(s):  
Ronald Green ◽  
Aivars J. Lelis ◽  
Daniel B. Habersat
Keyword(s):  
Threshold Voltage ◽  
Gate Voltage ◽  
Gate Bias ◽  
Electrical Measurements ◽  
Power Mosfets ◽  
Measurement Issues ◽  
Bias Stress ◽  
Bias Temperature Instability ◽  
Yield Test

This work focuses on measurement issues that affect the accuracy of positive bias temperature instability measurements of SiC power MOSFETs using a conventional sweep technique to characterize the threshold voltage, VT. Threshold-voltage shifts occurring during stress are readily recoverable during the measurement, resulting in an underestimation in VT degradation. Recovery of VT due to gate-stress relaxation before or during the measurement was a major source of measurement error that was mitigated by performing an immediate sweep down in gate voltage, VGS, from the stress bias toward threshold. Allowing the gate bias to drop to zero just prior to measuring by sweeping VGS positively resulted in smaller observed degradation due to VT recovery. This result is important, especially in cases where the gate stress has to be completely removed before making any electrical measurements. The VT shift caused by bias stress can quickly recover and yield test results that underestimate the effect of the applied stress. A full recovery of VT was observed following a positive gate bias stress for conditions where the gate was either subject to a negative gate voltage for a few seconds, or when VGS was maintained at zero volts for several minutes.

1200 V SiC IE-UMOSFET with Low On-Resistance and High Threshold Voltage

2017 ◽  
Vol 897 ◽  
pp. 497-500 ◽  
Author(s):  
Shinsuke Harada ◽  
Yusuke Kobayashi ◽  
A. Kinoshita ◽  
N. Ohse ◽  
Takahito Kojima ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Voltage ◽  
Gate Oxide ◽  
Critical Issue ◽  
High Threshold ◽  
Trade Off ◽  
Negative Gate Voltage

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.

High Temperature Performance of 3C-SiC MOSFETs with High Channel Mobility

2012 ◽  
Vol 717-720 ◽  
pp. 1109-1112 ◽  
Author(s):  
Hidetsugu Uchida ◽  
Akiyuki Minami ◽  
Toyokazu Sakata ◽  
Hiroyuki Nagasawa ◽  
Motoki Kobayashi
Keyword(s):  
High Temperature ◽  
Temperature Dependence ◽  
Leakage Current ◽  
Gate Voltage ◽  
Bandgap Energy ◽  
Leakage Currents ◽  
Channel Mobility ◽  
Temperature Performance ◽  
Threshold Voltages ◽  
Negative Gate Voltage

Transistor performances of lateral and vertical 3C-SiC MOSFETs are investigated in the temperature range of 25 °C to 300 °C. Both types of MOSFETs operate up to 300 °C and the lateral MOSFETs possess peak channel mobility of more than 100 cm2/(Vs) even at 300 °C for the [110]- and [-110]-channel directions. In both MOSFETs, on-currents decrease monotonically and threshold voltages shift negatively as the temperature increases. The temperature dependence of on-currents in the lateral MOSFETs is weaker than that in the vertical MOSFETs. The leakage current at the negative gate voltage increases at above 200 °C. The activation energies calculated from the leakage currents at 200 °C and 300 °C are about half of the 3C-SiC bandgap energy of 2.3 eV.

Threshold Voltage Instabilities of Present SiC-Power MOSFETs under Positive Bias Temperature Stress

2016 ◽  
Vol 858 ◽  
pp. 481-484 ◽  
Author(s):  
Gerald Rescher ◽  
Gregor Pobegen ◽  
Tibor Grasser
Keyword(s):  
Temperature Stress ◽  
Threshold Voltage ◽  
Physical Property ◽  
Oxide Thickness ◽  
Positive Bias ◽  
Threshold Voltage Shift ◽  
Power Mosfets ◽  
Fundamental Physical Property ◽  
Bias Temperature Stress ◽  
Silicon Based

We study the threshold voltage (Vth) instability of commercially available silicon carbide (SiC) power MOSFETs or prototypes from four different manufacturers under positive bias temperature stress (PBTS). A positive bias near the Vth causes a threshold voltage shift of 0.7 mV per decade in time per nanometer oxide thickness in the temperature range between-50 °C and 150 °C. Recovery at +5 V after a 100 s +25 V gate-pulse causes a recovery between-1.5 mV/dec/nm and-1.0 mV/dec/nm at room temperature and is decreasing with temperature. All devices show similar stress, recovery and temperature dependent behavior indicating that the observed Vth instabilities are likely a fundamental physical property of the SiC-SiO2 system caused by electron trapping in near interface traps. It is important to note that the trapping is not causing permanent damage to the interface like H-bond-breakage in silicon based devices and is nearly fully reversible via a negative gate bias.

Radiation-Induced Trapped Charging Effects in SiC Power MOSFETs

2014 ◽  
Vol 778-780 ◽  
pp. 533-536 ◽  
Author(s):  
Ronald Green ◽  
Aivars J. Lelis ◽  
Damian P. Urciuoli ◽  
Marc Litz ◽  
James Carroll
Keyword(s):  
Threshold Voltage ◽  
Radiation Response ◽  
Thermal Treatments ◽  
Power Mosfets ◽  
Radiation Induced ◽  
Post Radiation ◽  
Oxide Traps ◽  
Bias Temperature Stress ◽  
Tunneling Distance ◽  
Positively Charged

Commercial SiC MOSFETs were exposed to ionizing radiation to characterize the radiation response and to compare the observed threshold voltage (VT) instability post-radiation exposure, with the VT instability following bias temperature stress (BTS) testing. As expected, a large number of positively charged oxide traps were present in these devices following irradiation, resulting in a significant negative VT shift. However, the observed VT instability following irradiation was much smaller than that for similarly processed devices exposed to a BTS. Irradiated devices subjected to unbiased thermal treatments experienced a significant annealing of trapped holes above 100 °C. However, isochronal annealing treatments did not significantly alter the number of switching oxide traps, suggesting that a large portion of the traps activated by irradiation may lie deeper within the SiO2, beyond the tunneling distance from the SiC.

Bias-Temperature-Stress Response of Commercially-Available SiC Power MOSFETs

2015 ◽  
Vol 821-823 ◽  
pp. 677-680 ◽  
Author(s):  
Ronald Green ◽  
Aivars J. Lelis ◽  
Mooro El ◽  
Daniel B. Habersat
Keyword(s):  
Stress Response ◽  
Temperature Stress ◽  
Threshold Voltage ◽  
Stress Condition ◽  
Negative Bias ◽  
Gate Bias ◽  
Strong Function ◽  
Power Mosfets ◽  
Bias Temperature Stress ◽  
The Stability

The stability of the threshold voltage of commercial SiC MOSFETs from two device manufactures has been evaluated and compared when subject to positive and negative bias-temperature-stress conditions. For both device groupings, the worse-case stress occurred under negative bias temperature conditions with VGS = –15 V and a stress temperature of 200 °C. Devices in the Vendor A grouping exhibited acceleration in their bias-temperature-stress response that occurred earlier in time as a strong function of stress-temperature and to a lesser degree on gate-bias magnitude. Devices in the Vendor B grouping showed some evidence of acceleration, but only for the worse-case stress condition. Threshold voltage shifts for this device group were very low and extremely stable, with recorded values below 0.4 V for most conditions.

Effect of SiC Power DMOSFET Threshold-Voltage Instability

2008 ◽  
Vol 1069 ◽  
Author(s):  
Aivars Lelis ◽  
D. Habersat ◽  
R. Green ◽  
A. Ogunniyi ◽  
M. Gurfinkel ◽  
...  
Keyword(s):  
Leakage Current ◽  
Threshold Voltage ◽  
Power Loss ◽  
Gate Oxide ◽  
Primary Effect ◽  
Bias Stress ◽  
Voltage Instability ◽  
Oxide Traps ◽  
State Resistance

ABSTRACTWe have performed bias-stress induced threshold-voltage instability measurements on fully processed 4-H SiC power DMOSFETs as a function of bias-stress time, field, and temperature and have observed similar instabilities to those previously reported for lateral SiC MOSFET test structures. This effect is likely due to electrons tunneling into and out of near-interfacial oxide traps that extend spatially into the gate oxide. As long as the threshold voltage is set high enough to preclude the onset of subthreshold drain leakage current in the blocking state, then the primary effect of this instability is to increase the on-state resistance. For well-behaved power DMOSFETs, this would increase the power loss by no more than a few percent.

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