The Effect of Charge Redistribution on Flat-Band Voltage Turnaround in 4H-SiC MOS Capacitors

2017 ◽  
Vol 897 ◽  
pp. 167-170
Author(s):  
Hamid Amini Moghadam ◽  
Sima Dimitrijev ◽  
Ji Sheng Han ◽  
Daniel Haasmann
Keyword(s):  
Room Temperature ◽  
Flat Band ◽  
Gate Bias ◽  
Charge Redistribution ◽  
Flat Band Voltage ◽  
Transitional Layer ◽  
Mos Capacitors ◽  
Voltage Instability ◽  
Polar Species ◽  
Different Temperatures

The existence of a turnaround in flat-band voltage shift of stressed MOS capacitors, fabricated on N-type 4H–SiC substrates, is reported in this paper. The turnaround is observed by room-temperature C–V measurements, after two minutes gate-bias stressing of the MOS capacitors at different temperatures. The existence of this turnaround effect demonstrates that a mechanism, in addition to the well-stablished tunneling to the near-interface oxide traps, is involved in the threshold voltage instability of 4H–SiC MOSFETs. This newly identified mechanism occurs due to charge redistribution of the compound polar species that exist in the SiO2–SiC transitional layer.

On the Origin of Threshold Voltage Instability under Operating Conditions of 4H-SiC n-Channel MOSFETs

2016 ◽  
Vol 858 ◽  
pp. 473-476 ◽  
Author(s):  
Gregor Pobegen ◽  
Julietta Weisse ◽  
Martin Hauck ◽  
Heiko B. Weber ◽  
Michael Krieger
Keyword(s):  
Threshold Voltage ◽  
Energy Barrier ◽  
Room Temperature ◽  
Operating Conditions ◽  
Electron Trapping ◽  
Gate Bias ◽  
Drain Voltage ◽  
Mos Capacitors ◽  
Voltage Instability ◽  
Order Of Magnitude

We report on the threshold voltage () instability under operating conditions after gate bias switches at constant drain voltage for n-MOSFETs fabricated on 4H silicon carbide (4H-SiC). This effect occurs at room temperature and close to the of the device. We show that the origin of the instability is electron trapping into SiO2 over an energy barrier of (0.3-0.4) eV. These traps show similarities to traps previously observed in 4H-SiC MOS capacitors and labelled near interface traps (NITs). Further, the density of the traps can be reduced by one order of magnitude through post-oxidation annealing in nitric oxide atmosphere.

Electrical Performances of Low Temperature Annealed Hafnium Oxide Deposited at Room Temperature

2006 ◽  
Vol 514-516 ◽  
pp. 58-62 ◽  
Author(s):  
Luís Pereira ◽  
Pedro Barquinha ◽  
Elvira Fortunato ◽  
Rodrigo Martins
Keyword(s):  
Dielectric Constant ◽  
Charge Density ◽  
Hafnium Oxide ◽  
Room Temperature ◽  
Flat Band ◽  
Interface Properties ◽  
Flat Band Voltage ◽  
Fixed Charge Density ◽  
Gas Atmosphere ◽  
Deposited Film

In this work, HfO2 was deposited by r.f. sputtering at room temperature and then annealed for different times at 200°C in a forming gas atmosphere. After annealing for 2 hours the HfO2 layers present a reduction on the flat band voltage of about 1 V, relatively to the as deposited film, decreasing from -2.23V down to -1.28 V. This means an improvement of the interface properties and a reduction on the oxide charge density from 1.33×1012 cm-2 to 7.62×1011 cm-2. The dielectric constant reaches a maximum of 18.3 after 5h annealing due to film’s densification. When annealing for longer times such as 10h a small degradation of the electrical properties is observed. After 10h annealing the dielectric constant, flat band voltage and fixed charge density are respectively, 14.9, -2.96 V and 1.64 ×1012 cm-2 and the leakage current also increases due to film’s crystallization.

Erratum: Effect of illumination and gate bias on flat-band voltage in plasma CVD Si-N on n-Si MIS structure

1981 ◽  
Vol 17 (22) ◽  
pp. 862
Author(s):  
M.U. Jeong ◽  
J. Shirafuji ◽  
Y. Inuishi ◽  
H. Yakushiji ◽  
K. Harada ◽  
...  
Keyword(s):  
Flat Band ◽  
Mis Structure ◽  
Gate Bias ◽  
Flat Band Voltage ◽  
Plasma Cvd

Characterization of Electronic Charged States of Silicon Nanocrystals as a Floating Gate in MOS Structures

2004 ◽  
Vol 830 ◽  
Author(s):  
Seiichi Miyazaki ◽  
Taku Shibaguchi ◽  
Mitsuhisa Ikeda
Keyword(s):  
Visible Light ◽  
Energy State ◽  
Floating Gate ◽  
Flat Band ◽  
Displacement Current ◽  
Light Illumination ◽  
Flat Band Voltage ◽  
Mos Capacitors ◽  
Symmetric Pattern ◽  
Visible Light Illumination

ABSTRACTWe have studied capacitance-voltage (C-V) and displacement current-voltage characteristics of MOS capacitors with Si nanocrystals embedded in the gate oxide as a floating gate in dark and under visible light illumination at room temperature to gain a better understanding of discrete charged states of the Si-dots floating gate. The Si-dots floating gate with a dot density of 2.8×1011cm-2 and an average dot size of 8nm was fabricated on ∼2.8nm-thick thermally-grown SiO2 as a tunnel oxide by the thermal decomposition of SiH4, and covered with 7.5nm-thick control oxide prepared by thermal oxidation of a-Si. C-V characteristics of Al-gate MOS capacitors on p-type and n-type Si(100) show unique hystereses due to the charging and discharging of the Si-dots floating gate with a symmetric pattern reflecting the Fermi level of the substrate, which enable us to rule out the contribution of traps with a specific energy state to the observed hystereses. For each of high-frequency C-V curves measured in dark, a single capacitance peak appears only around a flat-band voltage condition, which is attributed to the quick flat-band voltage shift caused by the collective emission of charges retaining in the Si-dots floating gate as confirmed from the corresponding displacement current peak. Under visible light illumination, another capacitance peak due to collective charge injection to the electrically neutral Si-dots floating gate becomes observable in the inversion condition governing the on-state of MOS FETs. Thus, the optimum bias conditions for dot-floating gate MOSFETs can be predicted from the capacitor characteristics measured under light illumination.

Low Density of Interface States in n-Type 4H-SiC MOS Capacitors Achieved by Nitrogen Implantation

2005 ◽  
Vol 483-485 ◽  
pp. 693-696 ◽  
Author(s):  
Florin Ciobanu ◽  
Gerhard Pensl ◽  
Valeri V. Afanas'ev ◽  
Adolf Schöner
Keyword(s):  
Vapour Deposition ◽  
Oxidation Process ◽  
Chemical Vapour ◽  
Interface States ◽  
Conduction Band Edge ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Nitrogen Implantation ◽  
Mos Capacitors ◽  
Density Of Interface States

A surface-near Gaussian nitrogen (N) profile is implanted into n-type 4H-SiC epilayers prior to a standard oxidation process. Depending on the depth of the oxidized layer and on the implanted N concentration, the density of interface states DIT determined in corresponding 4H-SiC MOS capacitors decreases to a minimum value of approx. 1010 cm-2eV-1 in the investigated energy range (EC-(0.1 eV to 0.6 eV)), while the flat-band voltage increases to negative values due to generated fixed positive charges. A thin surface-near layer, which is highly N-doped during the chemical vapour deposition growth, leads to a reduction of DIT only close to the conduction band edge.

The Meyer-Neldel Relation and Analysis of the Field-Effect In Amorphous Silicon

1986 ◽  
Vol 70 ◽  
Author(s):  
Ruud E. I. Schropp ◽  
Jan Snijder ◽  
Jan F. Verwey
Keyword(s):  
Thin Film ◽  
Activation Energy ◽  
Density Of States ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Flat Band ◽  
Gate Bias ◽  
Flat Band Voltage ◽  
Conventional Analysis ◽  
First Time

ABSTRACTThe dependence of the conductance prefactor on the activation energy in accordance with the Meyer-Neldel relation has been observed in a-Si:H, by measuring the temperature dependence of the field-effect in a-Si:H thin-film transistors. The Meyer-Neldel rule is for the first time properly taken into account in the analysis of the field-effect, thereby considering the non-uniform shift of the Fermi-level as induced by the gate bias. The analysis also yields the flat-band voltage, which is an important parameter in the density of states evaluation. The density of states is shown to be considerably overestimated in conventional analysis.

Study on NO Passivation on the Near Interface Electron and Hole Traps of n-Type 4H-SiC MOS Capacitors by Ultraviolet Light

2018 ◽  
Vol 924 ◽  
pp. 449-452 ◽  
Author(s):  
Yi Fan Jia ◽  
Hong Liang Lv ◽  
Xiao Yan Tang ◽  
Qing Wen Song ◽  
Yi Men Zhang ◽  
...  
Keyword(s):  
Nitric Oxide ◽  
Ultraviolet Light ◽  
Annealed Sample ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Mos Capacitors ◽  
Bias Stress ◽  
Mos Devices ◽  
Capacitance Voltage ◽  
Electron And Hole Traps

The characteristics of near interface electron and hole traps in n-type 4H-SiC MOS capacitors with and without nitric oxide (NO) passivation have been systematically investigated. The hysteresis of the bidirectional capacitance-voltage (C-V) and the shift of flat band voltage (Vfb) caused by bias stress (BS) with and without ultraviolet light (UVL) irradiation are used for studying the influence of near interface electron traps (NIETs) and near interface hole traps (NIHTs). Compared with Ar annealed process, NO passivation can effectively reduce the density of NIETs, but induce excess NIHTs in the SiC MOS devices. What’s worse is that part of the trapped hole cannot be released easily from the NIHTs in the NO annealed sample, which may act as the positive fixed charge and induce the negative shift of threshold voltage.

Effect of Post-Metallization Hydrogen Annealing on C-V Characteristic of Zirconia Grown Using Atomic Layer Deposition

2002 ◽  
Vol 745 ◽  
Author(s):  
Arpan Chakraborty ◽  
Anil U. Mane ◽  
S. A. Shivashankar ◽  
V. Venkataraman
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Flat Band ◽  
Hydrogen Annealing ◽  
Mos Capacitors ◽  
Hysteresis Width ◽  
Layer Deposition ◽  
Different Temperatures

ABSTRACTSubstantial amount of fixed charge present in most of the alternative gate dielectrics gives rise to large shifts in the flat-band voltage (VFB) and charge trapping and de-trapping causes hysterectic changes on voltage cycling. Both phenomena affect stable and reliable transistor operation. In this paper we have studied for the first time the effect of post-metallization hydrogen annealing on the C-V curve of MOS capacitors employing zirconia, one of the most promising gate dielectric. Samples were annealed in hydrogen ambient for up to 30 minutes at different temperatures ranging from room temperature to 400°C. C-V measurements were done after annealing at each temperature and the hysteresis width was calculated from the C-V curves. A minimum hysteresis width of ∼35 mV was observed on annealing the sample at 200°C confirming the excellent suitability of this dielectric.

Ge out-diffusion and its Effect on Electrical Properties in s-Si/SiGe Devices

2006 ◽  
Vol 912 ◽  
Author(s):  
Suresh Uppal ◽  
Mehdi Kanoun ◽  
Sanatan Chattopadhyay ◽  
Rimoon Agaiby ◽  
Sarah H. Olsen ◽  
...  
Keyword(s):  
Activation Energy ◽  
Layer Thickness ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Strained Si ◽  
Mos Capacitors ◽  
Exponential Factor ◽  
Strained Layer ◽  
Exponential Increase ◽  
Flatband Voltage

AbstractIn this paper we report on the quantification of Ge diffusion in strained Si/SiGe (s-Si/SiGe) structures for different Ge content in the SiGe virtual substrate. Using TCAD tools, the diffusivity has been calculated by varying pre-exponential factor and activation energy for Ge diffusion in s-Si and SiGe layers separately and obtaining a fit to the SIMS profiles. We observe an exponential and a linear dependence of pre-factor and activation energy for Ge diffusion in s-Si and SiGe, respectively, which is in agreement with literature. As a result of diffusion, the carrier confinement in thin strained layer reduces and the mobility is affected. Using C-V measurements on MOS capacitors fabricated along with devices, a shift in the flat band voltage has been observed and is attributed to a change in the interface trapped and fixed oxide charge. We observe a stronger effect of the variation of strained layer thickness than Ge content on the change in the flatband voltage. This observation is consistent with an exponential increase in Ge arriving at the interface with decrease in strained layer thickness.

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