Low Density of Interface States in n-Type 4H-SiC MOS Capacitors Achieved by Nitrogen Implantation

2005 ◽  
Vol 483-485 ◽  
pp. 693-696 ◽  
Author(s):  
Florin Ciobanu ◽  
Gerhard Pensl ◽  
Valeri V. Afanas'ev ◽  
Adolf Schöner
Keyword(s):  
Vapour Deposition ◽  
Oxidation Process ◽  
Chemical Vapour ◽  
Interface States ◽  
Conduction Band Edge ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Nitrogen Implantation ◽  
Mos Capacitors ◽  
Density Of Interface States

A surface-near Gaussian nitrogen (N) profile is implanted into n-type 4H-SiC epilayers prior to a standard oxidation process. Depending on the depth of the oxidized layer and on the implanted N concentration, the density of interface states DIT determined in corresponding 4H-SiC MOS capacitors decreases to a minimum value of approx. 1010 cm-2eV-1 in the investigated energy range (EC-(0.1 eV to 0.6 eV)), while the flat-band voltage increases to negative values due to generated fixed positive charges. A thin surface-near layer, which is highly N-doped during the chemical vapour deposition growth, leads to a reduction of DIT only close to the conduction band edge.

3C-SiC MOS Based Devices: From Material Growth to Device Characterization

2011 ◽  
Vol 679-680 ◽  
pp. 433-436 ◽  
Author(s):  
Jean Lorenzzi ◽  
Romain Esteve ◽  
Nikoletta Jegenyes ◽  
Sergey A. Reshanov ◽  
Adolf Schöner ◽  
...  
Keyword(s):  
Chemical Vapour Deposition ◽  
Vapour Deposition ◽  
Advanced Oxidation Process ◽  
Oxidation Process ◽  
Chemical Vapour ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Heteroepitaxial Growth ◽  
Mos Capacitors ◽  
Surface Polishing

In this work we report on the growth and preparation of 3C-SiC(111) material for metal-oxide-semiconductor (MOS) application. In order to achieve reasonable material quality to prepare MOS capacitors several and crucial steps are needed: 1) heteroepitaxial growth of high quality 3C-SiC(111) layer by vapour-liquid-solid mechanism on 6H-SiC(0001) substrate, 2) surface polishing, 3) homoepitaxial re-growth by chemical vapour deposition and 4) use of an advanced oxidation process combining plasma enhanced chemical vapour deposition (PECVD) SiO2 and short post-oxidation steps in wet oxygen. Combining all these processes the interface traps density (Dit)can be drastically decreased down to 1.2  1010 eV-1cm-2 at 0.63 eV below the conduction band. To our knowledge, these values are the best ever reported for SiC material in general and 3C-SiC in particular.

Influence of the Oxidation Temperature and Atmosphere on the Reliability of Thick Gate Oxides on the 4H-SiC C(000-1) Face

2008 ◽  
Vol 600-603 ◽  
pp. 597-602 ◽  
Author(s):  
Michael Grieb ◽  
Dethard Peters ◽  
Anton J. Bauer ◽  
Peter Friedrichs ◽  
Heiner Ryssel
Keyword(s):  
Interface State ◽  
Interface States ◽  
Oxide Semiconductor ◽  
Constant Current ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Gate Oxides ◽  
Order Of Magnitude ◽  
State Densities ◽  
Density Of Interface States

The reliability of thermal oxides grown on n-type 4H-SiC C(000-1) face wafer has been investigated. In order to examine the influence of different oxidation atmospheres and temperatures on the reliability, metal-oxide-semiconductor capacitors were manufactured and the different oxides were characterized by C-V measurements and constant-current-stress. The N2O-oxides show the smallest flat band voltage shift compared to the ideal C-V curve and so the lowest number of effective oxide charges. They reveal also the lowest density of interface states in comparison to the other oxides grown on the C(000-1) face, but it is still higher than the best oxides on the Si(000-1) face. Higher oxidation temperatures result in smaller flat band voltage shifts and lower interface state densities. Time to breakdown measurements show that the charge-to-breakdown value of 63% cumulative failure for the N2O-oxide on the C(000-1) face is more than one order of magnitude higher than the highest values measured on the Si(000-1) face. Therefore it can be concluded that a smaller density of interface states results in a higher reliability of the oxide.

scholarly journals Characterization of MOS Capacitors Fabricated on n-type 4H-SiC Implanted with Nitrogen at High Dose

2007 ◽  
Vol 556-557 ◽  
pp. 639-642 ◽  
Author(s):  
Antonella Poggi ◽  
Francesco Moscatelli ◽  
Yasuto Hijikata ◽  
Sandro Solmi ◽  
Michele Sanmartin ◽  
...  
Keyword(s):  
Interface State ◽  
Interface States ◽  
State Density ◽  
Conduction Band Edge ◽  
High Dose ◽  
Wet Oxidation ◽  
Nitrogen Implantation ◽  
High Concentration ◽  
Mos Capacitors ◽  
Wide Range

Aiming to minimize the interface state density, we fabricated MOS capacitors on n-type 4H-SiC by using wet oxidation of nitrogen implanted layers. We investigated a wide range of implantation dose, including a high dose able to amorphise a surface SiC layer with the intent to reduce the oxidation time. The oxide quality and the SiO2-SiC interface properties were characterized by capacitance-voltage measurements of the MOS capacitors. The proposed process, in which nitrogen is ion-implanted on SiC layer before a wet oxidation, is effective to reduce the density of interface states near the conduction band edge if a high concentration of nitrogen is introduced at the SiO2-SiC interface. We found that only the nitrogen implanted at the oxide-SiC interface reduces the interface states and we did not observe the generation of fixed positive charges in the oxide as a consequence of nitrogen implantation. Furthermore, the concentration of the slow traps evaluated from the Slow Trap Profiling technique was low and did not depend on the nitrogen implantation fluence.

The Effect of Charge Redistribution on Flat-Band Voltage Turnaround in 4H-SiC MOS Capacitors

2017 ◽  
Vol 897 ◽  
pp. 167-170
Author(s):  
Hamid Amini Moghadam ◽  
Sima Dimitrijev ◽  
Ji Sheng Han ◽  
Daniel Haasmann
Keyword(s):  
Room Temperature ◽  
Flat Band ◽  
Gate Bias ◽  
Charge Redistribution ◽  
Flat Band Voltage ◽  
Transitional Layer ◽  
Mos Capacitors ◽  
Voltage Instability ◽  
Polar Species ◽  
Different Temperatures

The existence of a turnaround in flat-band voltage shift of stressed MOS capacitors, fabricated on N-type 4H–SiC substrates, is reported in this paper. The turnaround is observed by room-temperature C–V measurements, after two minutes gate-bias stressing of the MOS capacitors at different temperatures. The existence of this turnaround effect demonstrates that a mechanism, in addition to the well-stablished tunneling to the near-interface oxide traps, is involved in the threshold voltage instability of 4H–SiC MOSFETs. This newly identified mechanism occurs due to charge redistribution of the compound polar species that exist in the SiO2–SiC transitional layer.

New Technique for Ohmic Formation

1996 ◽  
Vol 427 ◽  
Author(s):  
S. Hara ◽  
T. Teraji ◽  
H. Okushi ◽  
K. Kajimura
Keyword(s):  
Work Function ◽  
Barrier Height ◽  
Electronic States ◽  
Surface States ◽  
Interface States ◽  
Hot Water ◽  
Flat Band ◽  
Interface Charges ◽  
The Difference ◽  
Density Of Interface States

AbstractWe propose a new systematical method to control Schottky barrier heights of metal/semiconductor interfaces by controlling the density of interface electronic states and the number of charges in the states. The density of interface states is controlled by changing the density of surface electronic states, which is controlled by surface hydrogenation and flattening the surface atomically. We apply establishing hydrogen termination techniques using a chemical solution, pH controlled buffered HF or hot water. Also, slow oxidation by oxygen gas was used to flatten resultant semiconductor surfaces. The density of interface charges is changeable by controlling a metal work function. When the density of surface states is reduced enough to unpin the Fermi level, the barrier height is determined simply by the difference between the work function of a metal φm and the flat-band semiconductor ØsFB. In such an interface with the low density of interface states, an Ohmic contact with a zero barrier height is formed when we select a metal with φm < φsFB. We have already demonstrated controlling Schottky and Ohmic properties by changing the pinning degree on silicon carbide (0001) surfaces. Further, on an atomically-flat Si(111) surface with monohydride termination, we have observed the lowering of an Al barrier height.

Fabrication of 4H-SiC p-Channel MOSFET with High Channel Mobility

2006 ◽  
Vol 527-529 ◽  
pp. 1301-1304
Author(s):  
Mitsuo Okamoto ◽  
Mieko Tanaka ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda
Keyword(s):  
Valence Band ◽  
Oxidation Process ◽  
Gate Oxide ◽  
Interface States ◽  
Wet Oxidation ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Dry Oxidation ◽  
Low Threshold ◽  
P Type

We have fabricated inversion-type p-channel MOSFETs on 4H-SiC substrates. In this paper, influences of gate oxidation process on the properties of p-channel MOSFETs were investigated. The gate oxide was formed under these three conditions: (i) dry oxidation, (ii) dry oxidation following wet re-oxidation, and (iii) wet oxidation. The C-V measurements of p-type 4H-SiC MOS capacitors revealed that wet oxidation process reduced the interface states near the valence band. The p-channel MOSFET with low interface states near the valence band indicated low threshold voltage (Vth), high field effect channel mobility (μFE) and low subthreshold swing (S). We obtained 4H-SiC p-channel MOSFET with high μFE of 15.6cm2/Vs by using wet oxidation as gate oxidation process.

Interface States in 4H- and 6H-SiC MOS Capacitors: A Comparative Study between Conductance Spectroscopy and Thermal Dielectric Relaxation Current Technique

2009 ◽  
Vol 615-617 ◽  
pp. 497-500 ◽  
Author(s):  
Lars S. Løvlie ◽  
Ioana Pintilie ◽  
S. Kumar C.P. ◽  
Ulrike Grossner ◽  
Bengt Gunnar Svensson ◽  
...  
Keyword(s):  
Comparative Study ◽  
Dielectric Relaxation ◽  
Cross Section ◽  
Capture Cross Section ◽  
Interface States ◽  
Conduction Band Edge ◽  
Capture Cross ◽  
Mos Capacitors ◽  
Dry Oxidation ◽  
Good Agreement

The purpose of this work is to compare the density of shallow interface states (Dit) at the interface of SiO2/SiC MOS capacitors as deducted by the conductance spectroscopy (CS) and thermally dielectric relaxation current (TDRC) techniques. Both capacitors of 4H- and 6H-SiC (n-type) are investigated, and both ordinary dry oxidation and an improved industrial procedure have been employed. The two techniques are found to give rather good agreement for interface states located ≥0.3 eV below the conduction band edge (Ec) while for more shallow states vastly different distributions of Dit are obtained. Different reasons for these contradictory results are discussed, such as strong temperature and energy dependence of the capture cross section of the shallow interface states.

Characterization of Electronic Charged States of Silicon Nanocrystals as a Floating Gate in MOS Structures

2004 ◽  
Vol 830 ◽  
Author(s):  
Seiichi Miyazaki ◽  
Taku Shibaguchi ◽  
Mitsuhisa Ikeda
Keyword(s):  
Visible Light ◽  
Energy State ◽  
Floating Gate ◽  
Flat Band ◽  
Displacement Current ◽  
Light Illumination ◽  
Flat Band Voltage ◽  
Mos Capacitors ◽  
Symmetric Pattern ◽  
Visible Light Illumination

ABSTRACTWe have studied capacitance-voltage (C-V) and displacement current-voltage characteristics of MOS capacitors with Si nanocrystals embedded in the gate oxide as a floating gate in dark and under visible light illumination at room temperature to gain a better understanding of discrete charged states of the Si-dots floating gate. The Si-dots floating gate with a dot density of 2.8×1011cm-2 and an average dot size of 8nm was fabricated on ∼2.8nm-thick thermally-grown SiO2 as a tunnel oxide by the thermal decomposition of SiH4, and covered with 7.5nm-thick control oxide prepared by thermal oxidation of a-Si. C-V characteristics of Al-gate MOS capacitors on p-type and n-type Si(100) show unique hystereses due to the charging and discharging of the Si-dots floating gate with a symmetric pattern reflecting the Fermi level of the substrate, which enable us to rule out the contribution of traps with a specific energy state to the observed hystereses. For each of high-frequency C-V curves measured in dark, a single capacitance peak appears only around a flat-band voltage condition, which is attributed to the quick flat-band voltage shift caused by the collective emission of charges retaining in the Si-dots floating gate as confirmed from the corresponding displacement current peak. Under visible light illumination, another capacitance peak due to collective charge injection to the electrically neutral Si-dots floating gate becomes observable in the inversion condition governing the on-state of MOS FETs. Thus, the optimum bias conditions for dot-floating gate MOSFETs can be predicted from the capacitor characteristics measured under light illumination.

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