Analysis Self-Healing of Gate Leakage Current due to Oxide Traps to Improve Reliability of Gate Electrode

2017 ◽  
Vol 897 ◽  
pp. 541-544 ◽  
Author(s):  
Shintaroh Sato ◽  
Haruka Shimizu ◽  
Akio Shima ◽  
Yasuhiro Shimamoto

To achieve robust SiC-MOSFET, reliability of the gate insulator was investigated in terms of gate electrode edge treatment. Analytical calculation showed that r should be larger than the thickness of gate insulator to relax the electric field concentration. We obtained the rounded gate edge by dry oxidation at 1000°C, while oxidation at 800°C had it sharpened. Former samples exhibited low leakage current with Time-Zero-Dielectric-Breakdown (TZDB) measurement. Ig consisted of Fowler-Nordheim (FN) tunneling current for Vg > 0, and it includes excess components for Vg < 0. We confirmed that they occurred at the gate edge and that they coursed positively charged trap centers in oxide near poly-Si/SiO2 interface which caused local barrier lowering. Electron injection removed them by tunneling/recombination process, which followed tunneling-front model.

2006 ◽  
Vol 89 (20) ◽  
pp. 202908 ◽  
Author(s):  
Mi-Hwa Lim ◽  
KyongTae Kang ◽  
Ho-Gi Kim ◽  
Il-Doo Kim ◽  
YongWoo Choi ◽  
...  

2021 ◽  
Vol 285 ◽  
pp. 129120
Author(s):  
Wenxin Liang ◽  
Hongfeng Zhao ◽  
Xiaoji Meng ◽  
Shaohua Fan ◽  
Qingyun Xie

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.


2018 ◽  
Vol 65 (2) ◽  
pp. 680-686 ◽  
Author(s):  
Cheng-Jung Lee ◽  
Ke-Jing Lee ◽  
Yu-Chi Chang ◽  
Li-Wen Wang ◽  
Der-Wei Chou ◽  
...  

2021 ◽  
pp. 106413
Author(s):  
Yuexin Yang ◽  
Zhuohui Xu ◽  
Tian Qiu ◽  
Honglong Ning ◽  
Jinyao Zhong ◽  
...  

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