Analysis of Contaminated Oxide-Silicon Interfaces

2011 ◽  
Vol 178-179 ◽  
pp. 243-248
Author(s):  
Maria Luisa Polignano ◽  
Davide Codegoni ◽  
Luca Castellano ◽  
Stefano Greco ◽  
Gabriella Borionetti ◽  
...  
Keyword(s):  
Surface Segregation ◽  
Surface Recombination ◽  
Interface State ◽  
State Density ◽  
Surface Recombination Velocity ◽  
Organic Contamination ◽  
Conductance Method ◽  
The Impact ◽  
Silicon Interface ◽  
Dlts Spectra

Methods for the analysis of the oxide-silicon interface were compared for their ability to reveal metal segregation at the interface and organic contamination. The impact of these contaminations on surface recombination velocity measurements, on capacitance vs. voltage, conductance vs. voltage and capacitance vs. time measurements and on MOS-DLTS spectra was studied. Niobium-contaminated wafers were used as an example of metal surface segregation, because it was previously shown that niobium is prone to surface segregation. Interface state density measurements obtained by the conductance method showed a limited impact of niobium implantation. Vice versa significant effects were found in MOS-DLTS spectra. For what concerns organic contamination, MOS-DLTS showed the most significant effects from the point-of-view of the intrinsic properties of the silicon oxide - silicon interface, and GOI tests demonstrate a clear impact of the organic contamination on MOS capacitors oxide breakdown events.

Characterization of nitrided silicon-silicon dioxide interfaces

1999 ◽  
Vol 591 ◽  
Author(s):  
M. L. Polignano ◽  
M. Alessandri ◽  
D. Brazzelli ◽  
B. Crivelli ◽  
G. Ghidini ◽  
...  
Keyword(s):  
Surface State ◽  
Surface Recombination ◽  
State Density ◽  
Constant Current ◽  
Surface Recombination Velocity ◽  
State Reduction ◽  
Surface State Density ◽  
Recombination Velocity ◽  
Silicon Interface

ABSTRACTA newly-developed technique for the simultaneos characterization of the oxide-silicon interface properties and of bulk impurities was used for a systematic study of the nitridation process of thin oxides. This technique is based upon surface recombination velocity measurements, and does not require the formation of a capacitor structure, so it is very suitable for the characterization of as-grown interfaces.Oxides grown both in dry and in wet enviroments were considered, and nitridation processes in N2O and in NO were compared to N2 annealing processes. The effect of nitridation temperature and duration were also studied, and RTO/RTN processes were compared to conventional furnace nitridation processes.Surface recombination velocity was correlated with nitrogen concentration at the oxide-silicon interface obtained by Secondary Ion Mass Spectroscopy (SIMS) measurements. Surface recombination velocity (hence surface state density) decreases with increasing nitrogen pile-up at the oxide-silicon interface, indicating that in nitrided interfaces surface state density is limited by nitridation. NO treatments are much more effective than N2O treatments in the formation of a nitrogen-rich interface layer and, as a consequence, in surface state reduction.Surface state density was measured in fully processed wafers before and after constant current stress. After a complete device process surface states are annealed out by hydrogen passivation, however they are reactivated by the electrical stress, and surface state results after stress were compared with data of surface recombination velocity in as-processed wafers.

Optimization of the Specific On-Resistance of 4H-SiC BJTs

2006 ◽  
Vol 527-529 ◽  
pp. 1429-1432 ◽  
Author(s):  
S. Balachandran ◽  
T. Paul Chow ◽  
Anant K. Agarwal
Keyword(s):  
High Voltage ◽  
Minority Carrier ◽  
Surface Recombination ◽  
Surface Recombination Velocity ◽  
Bipolar Junction Transistors ◽  
Carrier Lifetimes ◽  
Minority Carrier Lifetimes ◽  
Recombination Velocity ◽  
The Impact

We evaluate the performance capabilities and limitations of high voltage 4H-SiC based Bipolar Junction Transistors (BJTs). Experimental forward characteristics of a 4kV BJT are studied and simulations are employed to determine the factors behind the higher than expected specific onresistance (Ron,sp) for the device. The impact of material (minority carrier lifetimes), processing (surface recombination velocity) and design (p contact spacing from the emitter mesa) parameters on the forward active performance of this device are discussed and ways to lower Ron,sp, below the unipolar level, and increase the gain (β) are examined.

Electrical Stability Impact of Gate Oxide in Channel Implanted SiC NMOS and PMOS Transistors

2017 ◽  
Vol 897 ◽  
pp. 513-516 ◽  
Author(s):  
Muhammad I. Idris ◽  
Ming Hung Weng ◽  
H.K. Chan ◽  
A.E. Murphy ◽  
Dave A. Smith ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Oxide ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Single Type ◽  
Electrical Stability ◽  
Wide Range ◽  
Flatband Voltage ◽  
The Impact

Operation of SiC MOSFETs beyond 300°C opens up opportunities for a wide range of CMOS based digital and analogue applications. However the majority of the literature focuses only on the optimization of a single type of MOS device (either PMOS or more commonly NMOS) and there is a lack of a comprehensive study describing the challenge of optimizing CMOS devices. This study reports on the impact of gate oxide performance in channel implanted SiC on the electrical stability for both NMOS and PMOS capacitors and transistors. Parameters including interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) and effective charge (NEFF) have been acquired from C-V characteristics to assess the effectiveness of the fabrication process in realising high quality gate dielectrics. The performance of SiC based CMOS transistors were analyzed by correlating the characteristics of the MOS interface properties, the MOSFET 1/f noise performance and transistor on-state stability at 300°C. The observed instability of PMOS devices is more significant than in equivalent NMOS devices. The results from MOS capacitors comprising interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) for both N and P MOS are in agreement with the expected characteristics of the respective transistors.

Improved Characteristics of 4H-SiC MISFET with AlON/Nitrided SiO2 Stacked Gate Dielectrics

2010 ◽  
Vol 645-648 ◽  
pp. 991-994 ◽  
Author(s):  
Takuji Hosoi ◽  
Yusuke Kagei ◽  
Takashi Kirino ◽  
Yuu Watanabe ◽  
Kohei Kozono ◽  
...  
Keyword(s):  
Combination Treatment ◽  
Field Effect Transistors ◽  
Interface State ◽  
Nitrogen Plasma ◽  
State Density ◽  
Gate Insulator ◽  
Process Conditions ◽  
Aluminum Oxynitride ◽  
Channel Mobility ◽  
The Impact

We investigated the impact of a combination treatment of nitrogen plasma exposure and forming gas annealing (FGA) for a thermally grown SiO2 layer on channel electron mobility in 4H-SiC metal-insulator-semiconductor field-effect-transistors (MISFETs) with and without deposited aluminum oxynitride (AlON) overlayers. This treatment was effective for improving the interface properties of nitrided SiO2/SiC structures formed by thermal oxidation in NOx ambient as well as pure SiO2/SiC structures. A channel mobility enhancement was perfectly consistent with a reduction in interface state density depending on the process conditions of the combination treatment, and a peak mobility of 26.9 cm2/Vs was achieved for the MISFETs with the nitrided SiO2 single dielectric layer. Comparable channel mobility was obtained with a gate insulator consisting of the AlON stacked on a thin nitrided SiO2 interlayer, indicating that both the combination treatment and the AlON/SiO2 stacked dielectrics can be integrated into the SiC MISFET fabrication processes.

Effect of Thermal Stability and Roughness on Electrical Properties of Tantalum Oxide Gates

1999 ◽  
Vol 567 ◽  
Author(s):  
G.B. Alers ◽  
L.A. Stirling ◽  
R.B. Vandover ◽  
J.P. Chang ◽  
D.J. Werder ◽  
...  
Keyword(s):  
High Temperature ◽  
Gate Dielectrics ◽  
Tantalum Oxide ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Effective Dielectric Constant ◽  
Leakage Currents ◽  
Temperature Plasma ◽  
The Impact

ABSTRACTGate dielectrics with an effective SiO2 thickness of 1.6 nm (100 Hz) have been fabricated using chemical vapor deposition of tantalum oxide directly on silicon. A low temperature plasma anneal process was used to passivate excess traps in the oxide layer and to avoid degradation of capacitance and leakage after high temperature processing. Stable capacitance-voltage characteristics were obtained after the plasma anneal with an interface state density of ∼ 1012 cm−2 before post metallization anneal. We have examined the impact of high temperature processes and crystallization on the roughness for 10nm – 50nm films of Ta2O5 films on Si and SiN. The impact of roughness on capacitance and leakage current is examined through calculations assuming a Gaussian distribution of thickness across the capacitor with two conductive contacts. It is found that when the rms roughness exceeds about 20% of the film thickness then an increase in capacitance is observed that can be mistaken as an effective dielectric constant increase. The increase in capacitance due to roughness is accompanied by an exponential increase in leakage currents that ultimately degrades the charge storage capacity of the oxide.

Enhanced Gate Oxide Reliability through Fluorine Incorporation and the Influence of Polysilicon Process Variations

1991 ◽  
Vol 225 ◽  
Author(s):  
K. P. MacWilliams ◽  
L. E. Lowry ◽  
S. T. Lin ◽  
M. Song ◽  
R. Cole ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Low Frequency ◽  
Process Variations ◽  
Interface State ◽  
State Density ◽  
Apparent Lack ◽  
Hot Carrier ◽  
Quality And Reliability ◽  
Fluorinated Oxides ◽  
The Impact

ABSTRACTThere has been some uncertainty as to the impact of fluorine (F) on SiO2 quality and reliability. Several laboratories have shown greatly enhanced quality and reliability with fluorinated oxides, while others have been unable to repeat the results. In addition, the laboratories which have shown enhanced reliability with the fluorinated oxides have differed in their interpretation of the mechanism by which the enhancement occurs. X-ray diffraction stress measurements, partial time dependent dielectric breakdown (TDDB) measurements, SIMS depth profiling, transmission electron microscopy, standard high/low frequency C-V measurements, and hot-carrier aging of variously processed MOSFETs have been used to investigate a variety of fluorinated films. We believe that the apparent lack of consistency of the effects of fluorine on MOSFET reliability between laboratories may be explained by slight variations in the gate polysilicon processing which result in variations in polysilicon morphology. The polysilicon morphology determines both mechanical stress and F diffusion which ultimately impacts interface state density and thus hot carrier reliability.

Influence of the Highly-Doped Drain Implantation and the Window Size on Defect Creation in p+/n Si1-XGex Source/Drain Junctions

2007 ◽  
Vol 131-133 ◽  
pp. 95-100
Author(s):  
M. Kamruzzaman Chowdhury ◽  
B. Vissouvanadin ◽  
Mireia Bargallo Gonzalez ◽  
N. Bhouri ◽  
Peter Verheyen ◽  
...  
Keyword(s):  
Current Density ◽  
Defect Formation ◽  
Strain Relaxation ◽  
Surface States ◽  
Window Size ◽  
Local Strain ◽  
Interface State ◽  
State Density ◽  
Transmission Electron ◽  
The Impact

This paper presents an investigation of the impact of a Highly Doped Drain (HDD) implantation after epitaxial deposition on Si1-xGex S/D junction characteristics. While the no HDD diodes exhibit the usual scaling of the leakage current density with Perimeter to Area (P/A) ratio, this is not the case for the HDD diodes, showing a smaller perimeter current density JP for smaller window size structures, corresponding with larger P/A. This points to a lower density of surface states at the Shallow Trench Isolation (STI)/silicon interface, which could result from a lower compressive stress. In order to examine the role of the HDD implantation damage, Transmission Electron Microscopy (TEM) inspections have been undertaken, which demonstrate the presence of stacking faults in small active SiGe regions. These defects give rise to local strain relaxation and, therefore, could be at the origin of the lower STI/Si interface state density. The window size effect then comes from the active area dependence of the implantation defect formation.

Forward Active and Blocking Performance of 4H-SiC Bipolar Junction Transistors

2005 ◽  
Vol 888 ◽  
Author(s):  
Santhosh Balachandran ◽  
T. Paul Chow ◽  
Anant Agarwal
Keyword(s):  
High Voltage ◽  
Minority Carrier ◽  
Surface Recombination ◽  
Current Gain ◽  
Surface Recombination Velocity ◽  
Bipolar Junction Transistors ◽  
Carrier Lifetimes ◽  
Minority Carrier Lifetimes ◽  
Recombination Velocity ◽  
The Impact

ABSTRACTWe evaluate the performance capabilities and limitations of high voltage 4H-SiC based Bipolar Junction Transistors (BJTs). Experimental forward characteristics of a 4kV BJT are studied and simulations are employed to determine the factors behind the higher than expected specific on-resistance (Ron,sp) for the device. The impact of material (minority carrier lifetimes), processing (surface recombination velocity) and design (p contact spacing from the emitter mesa) parameters on the forward active performance of this device are discussed and ways to lower Ron,sp, below the unipolar level, and increase the gain (β) are examined. A correlation between the open base blocking behavior (forward blocking) and the current gain (forward active) for 4H-SiC based high-voltage BJTs with lightly doped collector regions is presented and experimental device characteristics are utilized to verify our numerical analysis.

Sign in / Sign up

Export Citation Format

Share Document