Effect of Thermal Stability and Roughness on Electrical Properties of Tantalum Oxide Gates

1999 ◽  
Vol 567 ◽  
Author(s):  
G.B. Alers ◽  
L.A. Stirling ◽  
R.B. Vandover ◽  
J.P. Chang ◽  
D.J. Werder ◽  
...  
Keyword(s):  
High Temperature ◽  
Gate Dielectrics ◽  
Tantalum Oxide ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Effective Dielectric Constant ◽  
Leakage Currents ◽  
Temperature Plasma ◽  
The Impact

ABSTRACTGate dielectrics with an effective SiO2 thickness of 1.6 nm (100 Hz) have been fabricated using chemical vapor deposition of tantalum oxide directly on silicon. A low temperature plasma anneal process was used to passivate excess traps in the oxide layer and to avoid degradation of capacitance and leakage after high temperature processing. Stable capacitance-voltage characteristics were obtained after the plasma anneal with an interface state density of ∼ 1012 cm−2 before post metallization anneal. We have examined the impact of high temperature processes and crystallization on the roughness for 10nm – 50nm films of Ta2O5 films on Si and SiN. The impact of roughness on capacitance and leakage current is examined through calculations assuming a Gaussian distribution of thickness across the capacitor with two conductive contacts. It is found that when the rms roughness exceeds about 20% of the film thickness then an increase in capacitance is observed that can be mistaken as an effective dielectric constant increase. The increase in capacitance due to roughness is accompanied by an exponential increase in leakage currents that ultimately degrades the charge storage capacity of the oxide.

Fabrication of High Quality MOS Devices for Application in Hazardous Environments Based on RTP Gate Dielectrics with In Situ RTCVD of Polysilicon Gates

1993 ◽  
Vol 300 ◽  
Author(s):  
B. Fröschle ◽  
H.P. Bruemmer ◽  
W. Lang ◽  
K. Neumeier ◽  
P. Ramm
Keyword(s):  
Threshold Voltage ◽  
Gate Dielectrics ◽  
Chemical Vapor ◽  
Process Variations ◽  
Interface State ◽  
State Density ◽  
Breakdown Field ◽  
Polysilicon Gate ◽  
Radiation Induced

ABSTRACTProcess modules for MOS gate fabrication were developed which can be completed subsequently in one RTP reactor: atmospheric process sequences for gate oxides and oxynitrides as well as low pressure chemical vapor deposition of polysilicon (RTCVD). Prior to the Rapid Thermal Oxidation (RTO), the wafers were treated with a Rapid Thermal Cleaning process (RTC) in H2/Ar ambient. After the desoxidation step the RTO was done in O2/H2/Ar followed by an anneal (RTA) for the gate oxide or a nitridation in NH3 (RTN) and reoxidation for the oxynitrides, respectively. The polysilicon gate electrode was fabricated either by RTCVD in situ or in a conventional furnace reactor. The two-step RTCVD process resulted in a very good thickness uniformity for the polysilicon layers of 3% (3mm from the edge). The influence of the process variations on breakdown field, fixed oxide charge, interface state density, flatband voltage, and threshold voltage of the different types of gate dielectrics was investigated. The charges and voltages were determined by LF-HF CV measurements. In order to characterize the radiation tolerance of electronic devices, radiation induced flatband and threshold voltage shifts as well as the build up of interface charges were determined. The irradiation was performed at a Co - 60 gamma source. Breakdown fields in the range of 19 MV/cm, interface state densities of less than 109 eV−1cm−2, and radiation induced threshold voltage shifts below 0.1 V after 1.5 Mrad(Si) were obtained.

Fabrication of High Quality Mos Devices for Application in Hazardous Environments Based on Rtp Gate Dielectrics With in Situ Rtcvd of Polysilicon Gates

1993 ◽  
Vol 303 ◽  
Author(s):  
B. Fröschle ◽  
H.P. Bruemmer ◽  
W. Lang ◽  
K. Neumeier ◽  
P. Ramm
Keyword(s):  
Threshold Voltage ◽  
Gate Dielectrics ◽  
Chemical Vapor ◽  
Process Variations ◽  
Interface State ◽  
State Density ◽  
Breakdown Field ◽  
Polysilicon Gate ◽  
Radiation Induced

ABSTRACTProcess modules for MOS gate fabrication were developed which can be completed subsequently in one RTP reactor: atmospheric process sequences for gate oxides and oxynitrides as well as low pressure chemical vapor deposition of polysilicon (RTCVD). Prior to the Rapid Thermal Oxidation (RTO), the wafers were treated with a Rapid Thermal Cleaning process (RTC) in H2/Ar ambient. After the desoxidation step the RTO was done in O2/H2/Ar followed by an anneal (RTA) for the gate oxide or a nitridation in NH3 (RTN) and reoxidation for the oxynitrides, respectively. The polysilicon gate electrode was fabricated either by RTCVD in situ or in a conventional furnace reactor. The two-step RTCVD process resulted in a very good thickness uniformity for the polysilicon layers of 3% (3mm from the edge). The influence of the process variations on breakdown field, fixed oxide charge, interface state density, flatband voltage, and threshold voltage of the different types of gate dielectrics was investigated. The charges and voltages were determined by LF-HF CV measurements. In order to characterize the radiation tolerance of electronic devices, radiation induced flatband and threshold voltage shifts as well as the build up of interface charges were determined. The irradiation was performed at a Co - 60 gamma source. Breakdown fields in the range of 19 MV/cm, interface state densities of less than 109 eV−2cm−2, and radiation induced threshold voltage shifts below 0.1 V after 1.5 Mrad(Si) were obtained.

Improved Electrical Properties and Thermal Stability of GeON Gate Dielectrics Formed by Plasma Nitridation of Ultrathin Oxides on Ge(100)

2011 ◽  
Vol 470 ◽  
pp. 152-157 ◽  
Author(s):  
Heiji Watanabe ◽  
Katsuhiro Kutsuki ◽  
Iori Hideshima ◽  
Gaku Okamoto ◽  
Takuji Hosoi ◽  
...  
Keyword(s):  
Thermal Stability ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Interface State ◽  
State Density ◽  
Air Exposure ◽  
Mos Capacitors ◽  
Plasma Nitridation ◽  
The Impact ◽  
Thermal Stability Of

We demonstrated the impact of plasma nitridation on thermally grown GeO2 for the purposes of obtaining high-quality germanium oxynitride (GeON) gate dielectrics. Physical characterizations revealed the formation of a nitrogen-rich surface layer on the ultrathin oxide, while keeping an abrupt GeO2/Ge interface without a transition layer. The thermal stability of the GeON layer was significantly improved over that of the pure oxide. We also found that although the GeO2 layer is vulnerable to air exposure, a nitrogen-rich layer suppresses electrical degradation and provides excellent insulating properties. Consequently, we were able to obtain Ge-MOS capacitors with GeON dielectrics of an equivalent oxide thickness (EOT) as small as 1.7 nm. Minimum interface state density (Dit) values of GeON/Ge structures, i.e., as low as 3 x 1011 cm-2eV-1, were successfully obtained for both the lower and upper halves of the bandgap.

Study of the impact of interface traps associated with SiNX passivation on AlGaN/GaN MIS-HEMTs

2022 ◽  
Author(s):  
Rijo Baby ◽  
Anirudh Venugopalrao ◽  
Hareesh Chandrasekar ◽  
Srinivasan Raghavan ◽  
Muralidharan Rangrajan ◽  
...  
Keyword(s):  
High Temperature ◽  
Gate Dielectric ◽  
Drain Current ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Temperature Dependent ◽  
The Impact ◽  
Surface Conduction ◽  
Magnitude Improvement

Abstract In this work, we show that a bilayer SiNx passivation scheme which includes a high-temperature annealed SiNx as gate dielectric, significantly improves both ON and OFF state performance of AlGaN/GaN MISHEMTs. From devices with different SiNx passivation schemes, surface and bulk leakage paths were determined. Temperature-dependent MESA leakage studies showed that the surface conduction could be explained using a 2-D variable range hopping mechanism along with the mid-gap interface states at the GaN(cap)/ SiNx interface generated due to the Ga-Ga metal like bonding states. It was found that the high temperature annealed SiNx gate dielectric exhibited the lowest interface state density and a two-step C-V indicative of a superior quality SiNx/GaN interface as confirmed from conductance and capacitance measurements. High-temperature annealing helps in the formation of Ga-N bonding states, thus reducing the shallow metal-like interface states. MISHEMT measurements showed a significant reduction in gate leakage and a 4-orders of magnitude improvement in the ON/OFF ratio while increasing the saturation drain current (IDS) by a factor of 2. Besides, MISHEMTs with 2-step SiNx passivation exhibited a relatively flat transconductance profile, indicative of lower interface states density. The dynamic Ron with gate and drain stressing measurements also showed about 3x improvements in devices with bilayer SiNx passivation.

Identification of Charging Effects in Plasma-Enhanced TEOS Deposition with Non-Contact Test Techniques

1998 ◽  
Author(s):  
Tomasz Brozek ◽  
James Heddleson
Keyword(s):  
Vapor Deposition ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Wafer Surface ◽  
Oxide Charge ◽  
Contact Test ◽  
Deposition Power ◽  
Oxide Deposition

Abstract Use of non-contact test techniques to characterize degradation of the Si-SiO2 system on the wafer surface exposed to a plasma environment have proven themselves to be sensitive and useful in investigation of plasma charging level and uniformity. The current paper describes application of the surface charge analyzer and surface photo-voltage tool to explore process-induced charging occurring during plasma enhanced chemical vapor deposition (PECVD) of TEOS oxide. The oxide charge, the interface state density, and dopant deactivation are studied on blanket oxidized wafers with respect to the effect of oxide deposition, power lift step, and subsequent annealing.

The Properties Of a-Si:H/c-Si Heterostructures Prepared By 55 kHz Pecvd For Solar Cell Application

1997 ◽  
Vol 485 ◽  
Author(s):  
B. G Budaguan ◽  
A. A. Aivazov ◽  
A. A. Sherchenkov ◽  
A. V Blrjukov ◽  
V. D. Chernomordic ◽  
...  
Keyword(s):  
Crystalline Silicon ◽  
Low Frequency ◽  
Reverse Current ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Solar Cell Application ◽  
Current Voltage ◽  
Frequency Plasma ◽  
Device Applications

AbstractIn this work a-Si:H/c-Si heterostructures with good electronic properties of a-Si:H were prepared by 55 kHz Plasma Enhanced Chemical Vapor Deposition (PECVD). Currentvoltage and capacitance-voltage characteristics of a-Si:H/c-Si heterostructures were measuredto investigate the influence of low frequency plasma on the growing film and amorphous silicon/crystalline silicon boundary. It was established that the interface state density is low enough for device applications (<2.1010 cm−2). The current voltage measurements suggest that, when forward biased, space-charge-limited current determines the transport mechanism in a- Si:H/c-Si heterostructures, while reverse current is ascribed to the generation current in a-Si:H and c-Si depletion layers.

Properties of Thin SiO2 Films with In-Situ Deposition of Poly Si Electrodes

1989 ◽  
Vol 146 ◽  
Author(s):  
Paihung Pan ◽  
Ahmad Kermani ◽  
Wayne Berry ◽  
Jimmy Liao
Keyword(s):  
Electrical Properties ◽  
Breakdown Strength ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
In Situ Deposition ◽  
Different Temperatures ◽  
Flatband Voltage ◽  
Si Films

ABSTRACTElectrical properties of thin (12 nm) SiO2 films with and without in-situ deposited poly Si electrodes have been studied. Thin SiO2 films were grown by the rapid thermal oxidation (RTO) process and the poly Si films were deposited by the rapid thermal chemical vapor deposition (RTCVD) technique at 675°C and 800°C. Good electrical properties were observed for SiO2 films with thin in-situ poly Si deposition; the flatband voltage was ∼ -0.86 V, the interface state density was < 2 × 1010/cm2/eV, and breakdown strength was > 10 MV/cm. The properties of RTCVD poly Si were also studied. The grain size was 10-60 rim before anneal and was 50-120 rim after anneal. Voids were found in thin (< 70 nm) RTCVD poly Si films. No difference in either SiO2 properties or poly Si properties was observed for poly Si films deposited at different temperatures.

Investigation of the off-current in amorphous silicon thin film transistors for SiO2 and SiNx. gate insulators

1996 ◽  
Vol 424 ◽  
Author(s):  
Jeong Hyun Kim ◽  
Woong Sik Choi ◽  
Chan Hee Hong ◽  
Hoe Sup Soh
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Gate Insulator ◽  
Defect States ◽  
Silicon Thin Film ◽  
Pressure Chemical

AbstractThe off current behavior of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) with an atmospheric pressure chemical vapor deposition (APCVD) silicon dioxide (SiO2) gate insulator were investigated at negative gate voltages. The a-Si:H TFT with SiO2 gate insulator has small off currents and large activation energy (Ea) of the off current compared to the a-Si:H TFT with SiNx gate insulator. The holes induced in the channel by negative gate voltage seem to be trapped in the defect states near the a-Si:H/SiO2 interface. The interface state density in the lower half of the band gap of a-Si:H/SiO2 appears to be much higher than that for a-Si:H/SiNx.

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