Board Level Reliability Enhancement for A Double-bump Wafer Level Chip Scale Package

This paper presents a nonlinear finite element analysis on board level solder joint reliability enhancement of a double-bump wafer level chip scale package (CSP). A viscoplastic constitutive relation is adopted for the solders to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the modified Coffin-Manson equation, which has been verified by experimental results using one of the double-bump wafer level CSP packages as the test vehicle. A series of parametric studies were performed by changing the Sn/Ag inner bump size (UBM pad size and standoff height), the eutectic Sn/Pb external solder joint size (pad size and standoff height), pitch, die thickness, and the encapsulant thickness. The results obtained from the modeling are useful to form design guidelines for board level reliability enhancement of the wafer level CSP packages.

Download Full-text

Board Level Reliability Study of Next Generation Large Die Wafer Level Chip Scale Package Structures

2018 International Wafer Level Packaging Conference (IWLPC) ◽

10.23919/iwlpc.2018.8573297 ◽

2018 ◽

Author(s):

Timo Henttonen ◽

Paul Mescher ◽

Doug Scott ◽

Han Park ◽

YongJae Ko ◽

...

Keyword(s):

Next Generation ◽

Wafer Level ◽

Reliability Study ◽

Chip Scale Package ◽

Board Level ◽

Board Level Reliability

Download Full-text

Low Profile and Large Size WLCSP in IoT Applications

International Symposium on Microelectronics ◽

10.4071/2380-4505-2019.1.000327 ◽

2019 ◽

Vol 2019 (1) ◽

pp. 000327-000332

Author(s):

Tom Tang ◽

Kuei Hsiao Kuo ◽

Victor Lin ◽

Kelly Chen ◽

J.Y. Chen ◽

...

Keyword(s):

High Performance ◽

Wafer Level ◽

Joint Reliability ◽

Large Size ◽

Low Profile ◽

Chip Scale Package ◽

Iot Devices ◽

Small Form Factor ◽

Board Level ◽

Board Level Reliability

Abstract Recently, Wafer Level Chip Scale Package (WLCSP) Package is being rapidly adopted in Internet of Things (IoT) and consumer mobile electronics due to its low profile, small form factor and relatively easy assembly process. WLCSP with large die size becomes the trend in fulfilling high performance product demands. However, the solder joint reliability performances of WLCSP is the key challenge and becomes critical as increasing die size, especially the size is larger than 6 × 6 mm2. There is also growing interest in low profile WLCSP packages to less than 300 microns, especially when they are placed in a limited space inside IoT devices. Thin wafers are fragile and must be supported over their full dimensions to prevent cracking and breakage. An increasingly popular approach to thin wafer handling involves grinding and taping thin wafers with in-line machines. A specific carry tape have been also developed for transferring thin wafers after thinning. In this paper, WLCSP board level reliability for both large die size and low profile was studied, a test vehicle used for the large WLCSP package testing has 350um ball pitch and fully populated array. In addition to board level reliability test simulation and data collection, processing challenges were discussed, as well as processing solutions for thin wafer handling.

Download Full-text

Investigations of Board-Level Drop Reliability of Wafer-Level Chip-Scale Packages

Journal of Electronic Packaging ◽

10.1115/1.2429717 ◽

2006 ◽

Vol 129 (1) ◽

pp. 105-108 ◽

Cited By ~ 10

Author(s):

Yi-Shao Lai ◽

Chang-Lin Yeh ◽

Ching-Chun Wang

Keyword(s):

Time Integration ◽

Implicit Time ◽

Wafer Level ◽

Excitation Scheme ◽

Implicit Time Integration ◽

Parametric Studies ◽

Support Excitation ◽

Board Level ◽

Board Level Reliability ◽

Die Thickness

We present in this paper parametric studies of board-level reliability of wafer-level chip-scale packages subjected to a specific pulse-controlled drop test condition. Eighteen experiment cells, constructed by varying joint pitch, die thickness, and die size, are proposed and examined numerically. The transient analysis follows the support excitation scheme and incorporates an implicit time integration solver. Numerical results indicate that the drop reliability of the package enhances as the die thickness as well as the die size decreases. Moreover, the package with smaller solder joints and a smaller joint pitch suffers a greater drop reliability concern.

Download Full-text

Improving WLCSP Reliability Through Solder Joint Geometry Optimization

International Symposium on Microelectronics ◽

10.4071/isom-2013-wa45 ◽

2013 ◽

Vol 2013 (1) ◽

pp. 000546-000550 ◽

Cited By ~ 5

Author(s):

Boyd Rogers ◽

Chris Scanlan

Keyword(s):

Solder Joint ◽

Thermal Cycling ◽

Printed Circuit Board ◽

Geometry Optimization ◽

Circuit Board ◽

Wafer Level ◽

Joint Geometry ◽

Chip Scale Package ◽

Large Platform ◽

Board Level

The effects of solder joint geometry on wafer-level chip-scale package reliability have been studied both through simulations and board level reliability testing. In reliability tests on a 3.9×3.9mm2 die, an enhancement of nearly 2× in thermal cycling reliability was achieved by optimizing the solder joint and under-bump pad stack. In particular, undersizing the printed circuit board pad to produce a more spherical solder joint and reducing the polymer via size under the bump appear to be very important for improving thermal cycling results. Data collected here shows that joint geometry changes can be implemented without compromising drop performance. Methods learned were applied to the qualification of a 6.0×6.0mm2 die, a large platform for WLCSP applications.

Download Full-text