Die to Die and Die To Wafer Bonding Solution for High Density, Fine Pitch Micro-Bumped Die

Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a Die-to-Die and Die-to-Wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10 μm micro-bumps at 20 μm pitch

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Combined Manufacture Methods for High Density LTCC Substrates: Thick Film Screen Printing, Ink Jet, Postfiring Thin Film Processes, and Laser-Drilled Fine Vias

Journal of Microelectronics and Electronic Packaging ◽

10.4071/1551-4897-6.1.6 ◽

2009 ◽

Vol 6 (1) ◽

pp. 6-12 ◽

Cited By ~ 3

Author(s):

Arne Albertsen ◽

Koji Koiwai ◽

Kyoji Kobayashi ◽

Tomonori Oguchi ◽

Katsumi Aruga

Keyword(s):

Thin Film ◽

Thick Film ◽

Screen Printing ◽

Flip Chip ◽

High Density ◽

Uv Laser ◽

Fine Pitch ◽

Ink Jet ◽

Printing Ink ◽

Base Substrate

This paper highlights the possible combination of technologies such as thick film screen printing, ink jet, and post-firing thin film processes in conjunction with laser-drilled fine vias to produce high-density, miniaturized LTCC substrates. To obtain the silver pattern on the inner layers, both conventional thick film printing and ink jet printing (using nano silver particle dispersed ink) were applied on the ceramic green sheets. The ink jet process made it possible to metallize fine lines with line/space = 30/30 μm. For interlayer connections, fine vias of 30 μm in diameter formed by UV laser were used. Then these sheets were stacked on top of each other and fired to obtain a base substrate. On this base substrate, fine copper patterns for flip chip mounting were formed by a thin film process. The surface finish consisted of a nickel passivation and a gold layer deposited by electroless plating. The combination of the three patterning processes for conducting traces and UV laser drilling of fine vias make it appear possible to realize fine pitch LTCC, for example, for flip chip device mounting.

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High density fine pitch Pb-free flip-chip interconnect assembly

Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003) ◽

10.1109/eptc.2003.1271492 ◽

2004 ◽

Cited By ~ 2

Author(s):

S.P.-S. Lim ◽

Chua Khoon Lam ◽

C. Lee ◽

Poi-Siong Teo

Keyword(s):

Flip Chip ◽

High Density ◽

Fine Pitch

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Assembly Challenges of High Density Large Fine Pitch Lead-Free, Flip-Chip Package

56th Electronic Components and Technology Conference 2006 ◽

10.1109/ectc.2006.1645619 ◽

2006 ◽

Cited By ~ 2

Author(s):

Ser Choong Chong ◽

Yeow Meng Tan ◽

Tai Chong Chai ◽

Samuel Lim ◽

Wai Yin Hnin ◽

...

Keyword(s):

Flip Chip ◽

High Density ◽

Lead Free ◽

Fine Pitch

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Epoxy Die Attach Combined With Face-Up Die Bonding for Improved XYZ Placement Accuracy

10.1115/ipack2021-69495 ◽

2021 ◽

Author(s):

Tadeh Avanessian ◽

Jim Clatterbaugh ◽

Robin L. Zinsmaster ◽

Leyla Hashemi

Keyword(s):

Flip Chip ◽

Coefficient Of Thermal Expansion ◽

Test Results ◽

Microelectronics Packaging ◽

Bond Failure ◽

Die Attach ◽

Before And After ◽

Placement Accuracy ◽

Die Bonding ◽

Heated Stage

Abstract Epoxy die attach is widely used in microcircuit assembly and enjoys advantages such as ease of deposition, fast curing, reworkability, and non-toxicity. These qualities also make it suitable for automated mass production. However, this method falls short when high placement accuracy is desired as the die can shift on uncured epoxy leading to die displacement from its original location. Gold to gold face-up bonding is another method utilized in microelectronics packaging given its proven bonding reliability and high placement accuracy for small devices. Nevertheless, it is difficult to achieve a reliable bond using this method for relatively larger devices. The nonplanarity of the bonding collet or the variation in the height of the gold bumps results in a tilted die attach and/or a weak bond between the die and the substrate. Moreover, CTE (Coefficient of Thermal Expansion) mismatch between the die, the gold bumps, and/or the substrate leads to bond failure due to temperature fatigue. This paper discusses a hybrid method to take advantage of the strengths of both methods mentioned above, culminating in a reliable process with high XYZ placement accuracy. To apply this method, epoxy is first dispensed on a gold-plated substrate. Using a flip chip machine, samples with plated gold bumps on their ground side are then placed on the substrate. The gold bumps are mainly used as targets and stand-offs to improve the placement accuracy and to control epoxy glue-line thickness. The force applied on the die, the time the force is applied, and the substrate temperature are controlled for optimum die attach. Moreover, along with the force applied by the vacuum tip, epoxy is partially cured on the flip chip machine heated stage before it is moved to an oven to complete the cure process. Die shear test results before and after temperature conditioning are compared with standard epoxy die attach and gold to gold face-up bonding for identical samples and the advantages are discussed.

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Influence of the Property of the Build-Up Package on Warpage at Flip Chip Assembly Process

2003 International Electronic Packaging Technical Conference and Exhibition, Volume 2 ◽

10.1115/ipack2003-35262 ◽

2003 ◽

Author(s):

Yukihiko Toyoda ◽

Yoichiro Kawamura ◽

Hiroyoshi Hiei ◽

Qiang Yu ◽

Tadahiro Shibutani ◽

...

Keyword(s):

Flip Chip ◽

Electronic Device ◽

New Product ◽

High Density ◽

Simulation Technique ◽

Assembly Process ◽

Reliability Problem ◽

Fine Pitch ◽

Flip Chip Assembly ◽

Single Material

High density and integrated packaging of electronic device requires fine pitch. This packaging causes reliability problem in electronic device. One of them, warpage of the package occurred at chip assembly process may affect reliability. Therefore, if the simulation at the time of a chip assembly process is possible, it will be able to evaluate warpage in advance. It is very effective for development of a new product. Then, in this paper, the build-up package is regarded as a single material and the simulation technique of accuracy warpage at the time of chip assembly is reported. Next it is investigated the simulation technique for package warpage at the chip assembly process. Finnaly, it analyzed about the properties which affect warpage.

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Reliability assessment of high density fine pitch lead-free flip chip package

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) ◽

10.1109/eptc.2004.1396647 ◽

2005 ◽

Cited By ~ 1

Author(s):

Ser Choong Chong ◽

Simon Ting ◽

Tan Yeow Meng ◽

Chai Tai Chong ◽

Srinivasamurthy Sampath ◽

...

Keyword(s):

Flip Chip ◽

Reliability Assessment ◽

High Density ◽

Lead Free ◽

Fine Pitch

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Processing and Reliability Assessment of Silicon Based, Integrated Ultra High Density Substrates

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2011dpc-tha23 ◽

2011 ◽

Vol 2011 (DPC) ◽

pp. 002272-002313

Author(s):

Brian J. Lewis ◽

D. F. Baldwin ◽

P. N. Houston ◽

B. Smith ◽

P. Kwok ◽

...

Keyword(s):

Flip Chip ◽

Reliability Assessment ◽

High Density ◽

Chip Technology ◽

Fine Pitch ◽

Characterization Study ◽

Alternative Materials ◽

Full Analysis ◽

Silicon Vias ◽

Silicon Based

High density interconnect (HDI) advances in substrate technology have allowed considerable improvements in processing more complex, compact devices. Chip Scale Packaging (CSP) and multi-chip modules (MCM) have continued to decrease in size and increase in functionality, moving closer to be more like flip chip technology. Improvements in wafer structuring allow for tremendous possibilities for device functionality; however a limit does exists on what traditional substrate fabrication methods will allow. A push in developing through silicon vias (TSVs) and use of alternative materials, other than organic or flex, are needed to enable new packaging technology developments. As needed, an alternative substrate has been developed that uses Silicon-based technology, photo-defined vias and the capability of semiconductor level routing density. It also includes the possibility to open cavities in the substrate to embed integrated die. This technology has opened up many possibilities for fabricating Ultra high density substrates from a US-based supplier that enables the use of integrated die, surface mount processing and fine pitch, multi-die placements. The following paper details the processing and reliability capabilities of this substrate technology. A comprehensive characterization study was conducted to evaluate the processing of units containing ultra-small SMT devices, intermixed with fine pitch, flip chip die. The units were also processed with traditional BGA balling, making them compatible with level 2, PCB level processes. Data will be shown with the results of the assembly analysis and subsequent reliability assessment of these units, showing a robust performance with thermal shock, uHAST and MSL level testing. A full analysis of the substrates structure will also be shown. The paper will show this technology's possibilities as a next generation substrate alternative.

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