Processing and Reliability Assessment of Silicon Based, Integrated Ultra High Density Substrates

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002272-002313
Author(s):  
Brian J. Lewis ◽  
D. F. Baldwin ◽  
P. N. Houston ◽  
B. Smith ◽  
P. Kwok ◽  
...  
Keyword(s):  
Flip Chip ◽  
Reliability Assessment ◽  
High Density ◽  
Chip Technology ◽  
Fine Pitch ◽  
Characterization Study ◽  
Alternative Materials ◽  
Full Analysis ◽  
Silicon Vias ◽  
Silicon Based

High density interconnect (HDI) advances in substrate technology have allowed considerable improvements in processing more complex, compact devices. Chip Scale Packaging (CSP) and multi-chip modules (MCM) have continued to decrease in size and increase in functionality, moving closer to be more like flip chip technology. Improvements in wafer structuring allow for tremendous possibilities for device functionality; however a limit does exists on what traditional substrate fabrication methods will allow. A push in developing through silicon vias (TSVs) and use of alternative materials, other than organic or flex, are needed to enable new packaging technology developments. As needed, an alternative substrate has been developed that uses Silicon-based technology, photo-defined vias and the capability of semiconductor level routing density. It also includes the possibility to open cavities in the substrate to embed integrated die. This technology has opened up many possibilities for fabricating Ultra high density substrates from a US-based supplier that enables the use of integrated die, surface mount processing and fine pitch, multi-die placements. The following paper details the processing and reliability capabilities of this substrate technology. A comprehensive characterization study was conducted to evaluate the processing of units containing ultra-small SMT devices, intermixed with fine pitch, flip chip die. The units were also processed with traditional BGA balling, making them compatible with level 2, PCB level processes. Data will be shown with the results of the assembly analysis and subsequent reliability assessment of these units, showing a robust performance with thermal shock, uHAST and MSL level testing. A full analysis of the substrates structure will also be shown. The paper will show this technology's possibilities as a next generation substrate alternative.

Combined Manufacture Methods for High Density LTCC Substrates: Thick Film Screen Printing, Ink Jet, Postfiring Thin Film Processes, and Laser-Drilled Fine Vias

2009 ◽  
Vol 6 (1) ◽  
pp. 6-12 ◽  
Author(s):  
Arne Albertsen ◽  
Koji Koiwai ◽  
Kyoji Kobayashi ◽  
Tomonori Oguchi ◽  
Katsumi Aruga
Keyword(s):  
Thin Film ◽  
Thick Film ◽  
Screen Printing ◽  
Flip Chip ◽  
High Density ◽  
Uv Laser ◽  
Fine Pitch ◽  
Ink Jet ◽  
Printing Ink ◽  
Base Substrate

This paper highlights the possible combination of technologies such as thick film screen printing, ink jet, and post-firing thin film processes in conjunction with laser-drilled fine vias to produce high-density, miniaturized LTCC substrates. To obtain the silver pattern on the inner layers, both conventional thick film printing and ink jet printing (using nano silver particle dispersed ink) were applied on the ceramic green sheets. The ink jet process made it possible to metallize fine lines with line/space = 30/30 μm. For interlayer connections, fine vias of 30 μm in diameter formed by UV laser were used. Then these sheets were stacked on top of each other and fired to obtain a base substrate. On this base substrate, fine copper patterns for flip chip mounting were formed by a thin film process. The surface finish consisted of a nickel passivation and a gold layer deposited by electroless plating. The combination of the three patterning processes for conducting traces and UV laser drilling of fine vias make it appear possible to realize fine pitch LTCC, for example, for flip chip device mounting.

Die to Die and Die To Wafer Bonding Solution for High Density, Fine Pitch Micro-Bumped Die

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002251-002284 ◽  
Author(s):  
Gilbert Lecarpentier ◽  
Joeri De Vos
Keyword(s):  
Wafer Bonding ◽  
Flip Chip ◽  
High Accuracy ◽  
High Density ◽  
Size Reduction ◽  
Direct Impact ◽  
3 Dimensional ◽  
Fine Pitch ◽  
Placement Accuracy ◽  
Die Bonding

Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a Die-to-Die and Die-to-Wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10 μm micro-bumps at 20 μm pitch

Fine pitch low-cost bumping for flip chip technology

2003 ◽  
Author(s):  
Szu-Wei Lu ◽  
Ruoh-Huey Uang ◽  
Kuo-Chuan Chen ◽  
Hsu-Tien Hu ◽  
Ling-Chen Kung ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Chip Technology ◽  
Fine Pitch

Assembly Challenges of High Density Large Fine Pitch Lead-Free, Flip-Chip Package

2006 ◽  
Author(s):  
Ser Choong Chong ◽  
Yeow Meng Tan ◽  
Tai Chong Chai ◽  
Samuel Lim ◽  
Wai Yin Hnin ◽  
...  
Keyword(s):  
Flip Chip ◽  
High Density ◽  
Lead Free ◽  
Fine Pitch

Advanced Silicon Interposer for High density and High Integration Electronic Packages

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000865-000905
Author(s):  
SATORU KUMOCHI ◽  
Sumio Koiwa ◽  
Kosuke Suzuki ◽  
Yoshitaka Fukuoka
Keyword(s):  
System Integration ◽  
High Density ◽  
High Resistivity ◽  
Through Silicon Vias ◽  
Passive Device ◽  
Fine Pitch ◽  
Mems Technology ◽  
Cte Mismatch ◽  
Silicon Vias ◽  
Electrical Loss

As electronic product becomes smaller and lighter with an increasing number of function← the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Interposers will be needed more complicated structure for 2.5D , 3D package and MEMS, OEMEMS new heterogeneous package structure Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. [1] This paper presents the demonstration of Silicon Interposers with fine pitch through Silicon vias(TSV),with embedded passive device. We have developed the TSV interposer with redistribution layers on both sides using MEMS technology, high aspect ratio deep etching technology and filled Cu plating with deep through holes for cost reduction and low electrical loss. The TSV interposer with 400μm thick high resistivity Si, obtained without backside processing use of carriers. Excellent through via reliability was demonstrated, due to double side thick polymer insulator that buffers the stress created by CTE mismatch between glass, copper vias and copper traces, and TSV at 200μm pitch passed 1000 thermal cycles from −55°C to 125°C. We have evaluated high frequency transmission characteristic of Si through hole by the measurement S21 parameter. Highly insulating TSV resulted in insertion loss of less than 1dB at 20GHz. Thin film SiN capacitor as embedded passive device was built in surface of TSV interposer by via first and via last method. The capacitance and leakage current of capacitor was measured and compared with two types of fabrication method.

Ultra-Thin and High-Density Packaging Using Both Sides Flip Chip Technology

2003 ◽  
Author(s):  
Kazuto Nishida ◽  
Kazumichi Shimizu ◽  
Michiro Yoshino ◽  
Hideo Koguchi ◽  
Nipon Taweejun
Keyword(s):  
Cross Section ◽  
Flip Chip ◽  
High Capacity ◽  
High Density ◽  
Thickness Direction ◽  
The Finite Element Method ◽  
Memory Card ◽  
Chip Technology ◽  
Chip Size ◽  
High Density Packaging

We have developed a high-density packaging technology by using a thin IC and a thin substrate and bonding it by new flip chip technology. Numerical analysis with the finite element method (FEM) as well experiments clearly showed that deflection of the IC and reliability were affected by the IC thickness. Consequently, reliability could be improved by reducing IC thickness. The dependency of the life in single-sided CSP and both-sided CSP on the thickness of IC and substrate could be expressed using a normal stress in the thickness direction and shear stress in the vertical cross section, respectively. Moreover, a both-sided flip chip approach solved the problem of warpage. A high-capacity memory card of 512 MB was put to practical use by applying these results. This increased the Si density by four times over that of a conventional chip-size package (CSP).

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