Influence of the Property of the Build-Up Package on Warpage at Flip Chip Assembly Process

High density and integrated packaging of electronic device requires fine pitch. This packaging causes reliability problem in electronic device. One of them, warpage of the package occurred at chip assembly process may affect reliability. Therefore, if the simulation at the time of a chip assembly process is possible, it will be able to evaluate warpage in advance. It is very effective for development of a new product. Then, in this paper, the build-up package is regarded as a single material and the simulation technique of accuracy warpage at the time of chip assembly is reported. Next it is investigated the simulation technique for package warpage at the chip assembly process. Finnaly, it analyzed about the properties which affect warpage.

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Corrections to "Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process"

IEEE Transactions on Components and Packaging Technologies ◽

10.1109/tcapt.2007.895649 ◽

2007 ◽

Vol 30 (2) ◽

pp. 359-359

Author(s):

Robert W. Kay ◽

Stoyan Stoyanov ◽

Greg P. Glinski ◽

Chris Bailey ◽

Marc P. Y. Desmulliez

Keyword(s):

Low Temperature ◽

Flip Chip ◽

Low Cost ◽

Assembly Process ◽

Stencil Printing ◽

Fine Pitch ◽

Flip Chip Assembly

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Ultra-Fine Pitch Stencil Printing for a Low Cost and Low Temperature Flip-Chip Assembly Process

IEEE Transactions on Components and Packaging Technologies ◽

10.1109/tcapt.2007.892085 ◽

2007 ◽

Vol 30 (1) ◽

pp. 129-136 ◽

Cited By ~ 23

Author(s):

Robert W. Kay ◽

Stephen Stoyanov ◽

Greg P. Glinski ◽

Chris Bailey ◽

Marc P. Y. Desmulliez

Keyword(s):

Low Temperature ◽

Flip Chip ◽

Low Cost ◽

Assembly Process ◽

Stencil Printing ◽

Fine Pitch ◽

Flip Chip Assembly

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Flip-Chip Flux Evolution

International Symposium on Microelectronics ◽

10.4071/2380-4505-2019.1.000115 ◽

2019 ◽

Vol 2019 (1) ◽

pp. 000115-000119 ◽

Cited By ~ 1

Author(s):

Andy Mackie ◽

Hyoryoon Jo ◽

Sze Pei Lim

Keyword(s):

Flip Chip ◽

Elevated Temperatures ◽

High Volume ◽

Automotive Electronics ◽

Assembly Process ◽

Surface Finishes ◽

Solder Bumps ◽

Thermocompression Bonding ◽

Advanced Packaging ◽

Flip Chip Assembly

Abstract Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.

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Combined Manufacture Methods for High Density LTCC Substrates: Thick Film Screen Printing, Ink Jet, Postfiring Thin Film Processes, and Laser-Drilled Fine Vias

Journal of Microelectronics and Electronic Packaging ◽

10.4071/1551-4897-6.1.6 ◽

2009 ◽

Vol 6 (1) ◽

pp. 6-12 ◽

Cited By ~ 3

Author(s):

Arne Albertsen ◽

Koji Koiwai ◽

Kyoji Kobayashi ◽

Tomonori Oguchi ◽

Katsumi Aruga

Keyword(s):

Thin Film ◽

Thick Film ◽

Screen Printing ◽

Flip Chip ◽

High Density ◽

Uv Laser ◽

Fine Pitch ◽

Ink Jet ◽

Printing Ink ◽

Base Substrate

This paper highlights the possible combination of technologies such as thick film screen printing, ink jet, and post-firing thin film processes in conjunction with laser-drilled fine vias to produce high-density, miniaturized LTCC substrates. To obtain the silver pattern on the inner layers, both conventional thick film printing and ink jet printing (using nano silver particle dispersed ink) were applied on the ceramic green sheets. The ink jet process made it possible to metallize fine lines with line/space = 30/30 μm. For interlayer connections, fine vias of 30 μm in diameter formed by UV laser were used. Then these sheets were stacked on top of each other and fired to obtain a base substrate. On this base substrate, fine copper patterns for flip chip mounting were formed by a thin film process. The surface finish consisted of a nickel passivation and a gold layer deposited by electroless plating. The combination of the three patterning processes for conducting traces and UV laser drilling of fine vias make it appear possible to realize fine pitch LTCC, for example, for flip chip device mounting.

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Die to Die and Die To Wafer Bonding Solution for High Density, Fine Pitch Micro-Bumped Die

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2012dpc-tha15 ◽

2012 ◽

Vol 2012 (DPC) ◽

pp. 002251-002284 ◽

Cited By ~ 1

Author(s):

Gilbert Lecarpentier ◽

Joeri De Vos

Keyword(s):

Wafer Bonding ◽

Flip Chip ◽

High Accuracy ◽

High Density ◽

Size Reduction ◽

Direct Impact ◽

3 Dimensional ◽

Fine Pitch ◽

Placement Accuracy ◽

Die Bonding

Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a Die-to-Die and Die-to-Wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10 μm micro-bumps at 20 μm pitch

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