Reliability assessment of high density fine pitch lead-free flip chip package

Author(s):  
Ser Choong Chong ◽  
Simon Ting ◽  
Tan Yeow Meng ◽  
Chai Tai Chong ◽  
Srinivasamurthy Sampath ◽  
...  
Author(s):  
Ser Choong Chong ◽  
Yeow Meng Tan ◽  
Tai Chong Chai ◽  
Samuel Lim ◽  
Wai Yin Hnin ◽  
...  
Keyword(s):  

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002272-002313
Author(s):  
Brian J. Lewis ◽  
D. F. Baldwin ◽  
P. N. Houston ◽  
B. Smith ◽  
P. Kwok ◽  
...  

High density interconnect (HDI) advances in substrate technology have allowed considerable improvements in processing more complex, compact devices. Chip Scale Packaging (CSP) and multi-chip modules (MCM) have continued to decrease in size and increase in functionality, moving closer to be more like flip chip technology. Improvements in wafer structuring allow for tremendous possibilities for device functionality; however a limit does exists on what traditional substrate fabrication methods will allow. A push in developing through silicon vias (TSVs) and use of alternative materials, other than organic or flex, are needed to enable new packaging technology developments. As needed, an alternative substrate has been developed that uses Silicon-based technology, photo-defined vias and the capability of semiconductor level routing density. It also includes the possibility to open cavities in the substrate to embed integrated die. This technology has opened up many possibilities for fabricating Ultra high density substrates from a US-based supplier that enables the use of integrated die, surface mount processing and fine pitch, multi-die placements. The following paper details the processing and reliability capabilities of this substrate technology. A comprehensive characterization study was conducted to evaluate the processing of units containing ultra-small SMT devices, intermixed with fine pitch, flip chip die. The units were also processed with traditional BGA balling, making them compatible with level 2, PCB level processes. Data will be shown with the results of the assembly analysis and subsequent reliability assessment of these units, showing a robust performance with thermal shock, uHAST and MSL level testing. A full analysis of the substrates structure will also be shown. The paper will show this technology's possibilities as a next generation substrate alternative.


2009 ◽  
Vol 6 (1) ◽  
pp. 6-12 ◽  
Author(s):  
Arne Albertsen ◽  
Koji Koiwai ◽  
Kyoji Kobayashi ◽  
Tomonori Oguchi ◽  
Katsumi Aruga

This paper highlights the possible combination of technologies such as thick film screen printing, ink jet, and post-firing thin film processes in conjunction with laser-drilled fine vias to produce high-density, miniaturized LTCC substrates. To obtain the silver pattern on the inner layers, both conventional thick film printing and ink jet printing (using nano silver particle dispersed ink) were applied on the ceramic green sheets. The ink jet process made it possible to metallize fine lines with line/space = 30/30 μm. For interlayer connections, fine vias of 30 μm in diameter formed by UV laser were used. Then these sheets were stacked on top of each other and fired to obtain a base substrate. On this base substrate, fine copper patterns for flip chip mounting were formed by a thin film process. The surface finish consisted of a nickel passivation and a gold layer deposited by electroless plating. The combination of the three patterning processes for conducting traces and UV laser drilling of fine vias make it appear possible to realize fine pitch LTCC, for example, for flip chip device mounting.


2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002251-002284 ◽  
Author(s):  
Gilbert Lecarpentier ◽  
Joeri De Vos

Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a Die-to-Die and Die-to-Wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10 μm micro-bumps at 20 μm pitch


2013 ◽  
Vol 2013 (1) ◽  
pp. 000420-000423
Author(s):  
Kwang-Seong Choi ◽  
Ho-Eun Bae ◽  
Haksun Lee ◽  
Hyun-Cheol Bae ◽  
Yong-Sung Eom

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.


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