NCP (Non Conductive Paste) for Narrow Gap Flip Chip Package and TSV Package

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-34
Author(s):  
Hidenori Abe ◽  
Tomoya Masuda ◽  
Yuko Kondo ◽  
Hiroshi Takahashi
Keyword(s):  
Flip Chip ◽  
Material Design ◽  
Bonding Process ◽  
Temperature Cycle ◽  
Thermal Compression ◽  
Bonding Area ◽  
Level 3 ◽  
Temperature Cycle Test ◽  
Short Time ◽  
Low K

Pre-applied process followed by mounting chip and underfill at the same time is considered as promising underfill process for coming finer pitch and narrower gap flip chip package with Cu pillar and also TSV package with micro bumps. On the other hand, conventional mass reflow could introduce too much stress on low-k chip with advanced node. Pre-applied underfill process can reduce stress on low-k chip by dispersing stress into underfill material at the connection with thermal compression bonding process. One of the challenges of thermal compression bonding process with NCP is trapping material and poor connection at the bonding area. Creeping and voiding are other challenges for NCP. This presentation reports material design of a new NCP, features, and reliability results. Our newly developed NCP material was dispensed smoothly, and didn't cause creeping up on the backside of the chip. While low thixotropic NCP tends to create voids because of easier NCP spreading out when chip is mounted, this NCP material showed good performance in terms of voiding because of high thixotropic index, less spreading out even under heating condition (<80degC) and reduced out gas in this material. We explored appropriate fluxing material inside NCP, optimized filler size and distribution, viscosity, thixotropic index and curing behavior to avoid trapping issue. Cross-section of bonding area showed sufficient solder wetting and this NCP material had excellent connectivity. In addition, this NCP material can be processed in a very short time. The TV underfilled by this NCP material was subjected to reliability tests, and passed 5x reflow test (JEDEC standard preconditioning Level 3), 1000 cycles of temperature cycle test (−55degC to 125degC), and 200 hours of biased HAST test (135degC/85%RH/1.3V).

Development of Lead-Free Flip Chip Package and Its Reliability

2003 ◽  
Author(s):  
Jeffrey C. B. Lee ◽  
Sting Wu ◽  
H. L. Chou ◽  
Yi-Shao Lai
Keyword(s):  
Failure Mode ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Wire Bonding ◽  
Point Of View ◽  
Lead Free ◽  
Temperature Cycle ◽  
Snagcu Solder ◽  
Temperature Cycle Test

SnAgCu solder used in laminate package like PBGA and CSP BGA to replace eutectic SnPb as interconnection has become major trend in the electronic industry. But unlike well-known failure mode of wire bonding package, flip chip package with SnAgCu inner solder bump and external solder ball as electrical interconnection present a extremely different failure mode with wire-bonding package from a point of view in material and process. In this study, one 16mm×16mm 3000 I/O SnAgCu wafer bumping using screen-printing process was explored including the effects of reflow times, high temperature storage life (HTSL) and temperature cycle test (TCT) on bump shear strength. Furthermore, the qualified wafer bumping is assembled by flip chip assembly with various underfill material and specific organic build-up substrate, then is subject to MSL4/260°C precondition and temperature cycle test to observe the underfill effect on SnAgCu bump protection and solder joint life. Various failure modes in the flip chip package like solder bump, underfill and UBM and so on, will be scrutinized with SEM. And finally, best material combination will be addressed to make the lead free flip package successful.

Development of thin package using the glass carrier substrate

2015 ◽  
Vol 2015 (1) ◽  
pp. 000087-000091
Author(s):  
Jun Onohara ◽  
Takashi Fujita ◽  
Yoshito Akutagawa
Keyword(s):  
Injection Molding ◽  
Adhesive Layer ◽  
Temperature Cycle ◽  
Effective Solution ◽  
Thermal Compression ◽  
Temperature Cycle Test

“The glass carrier substrate” formed on support glass using conventional build-up substrate technologies is developed. This substrate is ultrathin, and is suitable for the applications that thinner packages are highly demanded, such as for mobiles. The advantage of glass as the carrier for the substrate is that the CTE of glass is close to that of silicon. The CTE matching of glass with silicon enables the narrow pitch mounting, because of reduced distortions between the chip and the substrate. When the chip is bonded on the substrate, glass is still combined with the substrate as the carrier. After chip bonding, the substrate can easily peeled off with laser irradiating through glass due to the characters of adhesive layer. To verify the advantage, we prepared the thin substrate and made a connection with a narrow pitch (50um) bump chip, by means of Thermal Compression Bonding with non-conductive paste. The process of injection molding was used for packaging the substrate. We evaluated the reliability of the thin package, by temperature cycle test (JEDEC MSL-3+Cond.B). It was confirmed that the package passed the criteria. It is convinced that the package with glass carrier substrate is an effective solution for making thinner packages.

Reliability of Multi-Layer Wiring Board Embedded with Two Dies in Stacked Configuration

2014 ◽  
Vol 2014 (1) ◽  
pp. 000161-000164 ◽  
Author(s):  
Koji Munakata ◽  
Nobuki Ueta ◽  
Masahiro Okamoto ◽  
Kumi Onodera ◽  
Kazu Itoi ◽  
...  
Keyword(s):  
Stress Test ◽  
Base Material ◽  
Single Step ◽  
Temperature Cycle ◽  
Wafer Level ◽  
Level 3 ◽  
Semiconductor Packages ◽  
Wiring Board ◽  
Temperature Cycle Test ◽  
Electrical Connections

As electronic devices decrease in size and increase in functionality, their surface-mount components grow in number. This trend created a need for securing appropriate space in and on a wiring board to accommodate necessary components. Conventionally, dies are mounted on a wiring board. Much effort is spent for space savings. We have come up with a structure to include dies inside a wiring board and succeeded in fabricating the board in which two dies are embedded in a 3D stacked configuration. This new structure shrinks the foot print size and thus contributes to higher density and functionality of a semiconductor package and SiP. In addition, since the base material is polyimide, this board is as thin as 0.45 mm with two WLP (Wafer Level Package) dies (3 mm x 3 mm x 0.085 mm) embedded between any of 9 wiring layers. The module level warpage on the both sides of this board is 0.035 mm, so it is possible to mount components on the both sides. This board was fabricated based on our WABE technologyTM (Wafer and Board level Embedding technology) that includes a single step co-laminating process and embedded technology using conductive-paste-filled vias for establishing z-axis interlayer electrical connections. The conductive paste formed intermetallic compound with the copper foil and the via showed stable electrical connections by metallic bonding. Copper pads were fabricated on the dies by a wafer level process in advance. The polyimide-based films were laminated with adhesive and the dies were embedded. At the same time, electrical connections were established. This method enables the production of an embedded board by one-time curing after the alignment and fixing of necessary layers. We applied this method to the new structure that includes two dies in a 3D configuration to achieve a simple fabrication process using the single step co-lamination process. We evaluated the reliability of this board as below. The electric resistance was measured after various reliability tests including Temperature Cycle Test, Temperature Humidity Bias Test and Highly Accelerated Stress Test following a moisture sensitive reflow test (based on IPC/JEDEC J-STD-020 Level 3). From the results, there were no major defects observed in the test boards, either visually or functionally. This two-die embedding technology helps to realize the miniaturization and contribute to higher functionality of semiconductor packages and SiPs.

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