Reliability of Multi-Layer Wiring Board Embedded with Two Dies in Stacked Configuration

2014 ◽  
Vol 2014 (1) ◽  
pp. 000161-000164 ◽  
Author(s):  
Koji Munakata ◽  
Nobuki Ueta ◽  
Masahiro Okamoto ◽  
Kumi Onodera ◽  
Kazu Itoi ◽  
...  
Keyword(s):  
Stress Test ◽  
Base Material ◽  
Single Step ◽  
Temperature Cycle ◽  
Wafer Level ◽  
Level 3 ◽  
Semiconductor Packages ◽  
Wiring Board ◽  
Temperature Cycle Test ◽  
Electrical Connections

As electronic devices decrease in size and increase in functionality, their surface-mount components grow in number. This trend created a need for securing appropriate space in and on a wiring board to accommodate necessary components. Conventionally, dies are mounted on a wiring board. Much effort is spent for space savings. We have come up with a structure to include dies inside a wiring board and succeeded in fabricating the board in which two dies are embedded in a 3D stacked configuration. This new structure shrinks the foot print size and thus contributes to higher density and functionality of a semiconductor package and SiP. In addition, since the base material is polyimide, this board is as thin as 0.45 mm with two WLP (Wafer Level Package) dies (3 mm x 3 mm x 0.085 mm) embedded between any of 9 wiring layers. The module level warpage on the both sides of this board is 0.035 mm, so it is possible to mount components on the both sides. This board was fabricated based on our WABE technologyTM (Wafer and Board level Embedding technology) that includes a single step co-laminating process and embedded technology using conductive-paste-filled vias for establishing z-axis interlayer electrical connections. The conductive paste formed intermetallic compound with the copper foil and the via showed stable electrical connections by metallic bonding. Copper pads were fabricated on the dies by a wafer level process in advance. The polyimide-based films were laminated with adhesive and the dies were embedded. At the same time, electrical connections were established. This method enables the production of an embedded board by one-time curing after the alignment and fixing of necessary layers. We applied this method to the new structure that includes two dies in a 3D configuration to achieve a simple fabrication process using the single step co-lamination process. We evaluated the reliability of this board as below. The electric resistance was measured after various reliability tests including Temperature Cycle Test, Temperature Humidity Bias Test and Highly Accelerated Stress Test following a moisture sensitive reflow test (based on IPC/JEDEC J-STD-020 Level 3). From the results, there were no major defects observed in the test boards, either visually or functionally. This two-die embedding technology helps to realize the miniaturization and contribute to higher functionality of semiconductor packages and SiPs.

Optical Stressing of 4H-SiC Material and Devices

2018 ◽  
Vol 924 ◽  
pp. 196-199 ◽  
Author(s):  
Birgit Kallinger ◽  
Daniel Kaminzky ◽  
Patrick Berwian ◽  
Jochen Friedrich ◽  
Steffen Oppel
Keyword(s):  
Stress Test ◽  
Stacking Faults ◽  
Base Material ◽  
Structural Defects ◽  
Reliability Testing ◽  
Uv Laser ◽  
Stress Tests ◽  
Wafer Level ◽  
Electrical Stress ◽  
Established Technique

Electrical testing with regard to bipolar degradation of high voltage SiC devices cannot be done on wafer level, but only expensively after module assembly. We show that 4H-SiC material can be optically stressed by applying high UV laser intensities, i.e. bipolar degradation as in electrical stress tests can be provoked on wafer level. Therefore, optical stressing can be used for control measurements and reliability testing. Different injection (=stress) levels have been used similar to the typical doping level of the base material and similar to the established electrical stress test. The analysis of degradation is done by photoluminescence imaging which is a well-established technique for revealing structural defects such as Basal Plane Dislocations (BPDs) and stacking faults (SFs) in 4H-SiC epiwafers and partially processed devices.

TCT Reliability of Organic Passivation Layer for WLCSP

2015 ◽  
Vol 2015 (1) ◽  
pp. 000505-000509 ◽  
Author(s):  
Mitsuru Fujita ◽  
Atsushi Fujii ◽  
Shuji Shimoda ◽  
Yoshiharu Kariya
Keyword(s):  
Passivation Layer ◽  
Fatigue Properties ◽  
Temperature Cycle ◽  
Wafer Level ◽  
Element Analysis ◽  
Joint Reliability ◽  
Solder Bumps ◽  
Temperature Cycle Test ◽  
Board Level ◽  
Interconnect Technology

Wafer level chip scale packages (WLCSP) have been increasingly used in portable electronic products such as mobile phones. Solder bumps with redistribution layer (RDL) are typical interconnect technology for WLCSP applications. One of the major concerns in joint reliability is the failure by temperature cyclic stresses. In addition, in terms of heat tolerance or device yields, process temperature of RDL dielectric is limited around 200deg.C in some packaging applications. According to our board level reliability test for temperature cycle test (TCT), photosensitive polyimide (PI) which is 200deg.C curable material has lower fail rate than polybenzoxazole (PBO) by TCT. In this study, we compared the actual board level test and Finite Element Analysis (FEA) during temperature cycle test, and correlated the mechanical and fatigue properties of passivation layer material with TCT reliability.

NCP (Non Conductive Paste) for Narrow Gap Flip Chip Package and TSV Package

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-34
Author(s):  
Hidenori Abe ◽  
Tomoya Masuda ◽  
Yuko Kondo ◽  
Hiroshi Takahashi
Keyword(s):  
Flip Chip ◽  
Material Design ◽  
Bonding Process ◽  
Temperature Cycle ◽  
Thermal Compression ◽  
Bonding Area ◽  
Level 3 ◽  
Temperature Cycle Test ◽  
Short Time ◽  
Low K

Pre-applied process followed by mounting chip and underfill at the same time is considered as promising underfill process for coming finer pitch and narrower gap flip chip package with Cu pillar and also TSV package with micro bumps. On the other hand, conventional mass reflow could introduce too much stress on low-k chip with advanced node. Pre-applied underfill process can reduce stress on low-k chip by dispersing stress into underfill material at the connection with thermal compression bonding process. One of the challenges of thermal compression bonding process with NCP is trapping material and poor connection at the bonding area. Creeping and voiding are other challenges for NCP. This presentation reports material design of a new NCP, features, and reliability results. Our newly developed NCP material was dispensed smoothly, and didn't cause creeping up on the backside of the chip. While low thixotropic NCP tends to create voids because of easier NCP spreading out when chip is mounted, this NCP material showed good performance in terms of voiding because of high thixotropic index, less spreading out even under heating condition (<80degC) and reduced out gas in this material. We explored appropriate fluxing material inside NCP, optimized filler size and distribution, viscosity, thixotropic index and curing behavior to avoid trapping issue. Cross-section of bonding area showed sufficient solder wetting and this NCP material had excellent connectivity. In addition, this NCP material can be processed in a very short time. The TV underfilled by this NCP material was subjected to reliability tests, and passed 5x reflow test (JEDEC standard preconditioning Level 3), 1000 cycles of temperature cycle test (−55degC to 125degC), and 200 hours of biased HAST test (135degC/85%RH/1.3V).

Revealing Metal Corrosion Failures Using Wafer Level Temperature Cycle Stress Testing

2005 ◽  
Author(s):  
J.M. Duffalo ◽  
J.E. Staszkow ◽  
J.A. Chan ◽  
P.D. Egelhoff ◽  
H.A. Pollack ◽  
...  
Keyword(s):  
Stress Testing ◽  
Metal Corrosion ◽  
Temperature Cycle ◽  
Wafer Level

Robust Reliability Performance of Large size eWLB (Fan-out WLP)

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001438-001457 ◽  
Author(s):  
Seung Wook Yoon
Keyword(s):  
Form Factor ◽  
Dielectric Materials ◽  
Structural Defects ◽  
Temperature Cycle ◽  
Wafer Level ◽  
Component Level ◽  
Wafer Level Packaging ◽  
Large Size ◽  
Reliability Performance ◽  
Robust Reliability

With reducing form-factor and functional integration of mobile devices, Wafer Level Packaging (WLP) is attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP, it is more optimal and promising solution compared to fan-in WLP, because it can offer greater flexibility in design of more IOs, multi-chips, heterogeneous integration and 3D SiP. eWLB (embedded wafer level packaging) is a type of fan-out WLP enabling applications that require smaller form-factor, excellent heat dissipations, thin package profile as it has the potential to evolve in various configurations with proven manufacturing capacity and production yield. This paper discusses the recent advancements of robust reliability performance of large size eWLB. It will also highlight the recent achievement of enhanced component level reliability with advanced dielectric materials. After a parametric study and mechanical simulations, new advanced materials were selected and applied to eWLB. Standard JEDEC tests were carried out to investigate component level reliability of large size (9x9~14x14mm2) test vehicles and both destructive/non-destructive analysis were performed to investigate potential structural defects. Daisychain test vehicles were also tested for drop and TCoB (Temperature Cycle on Board) reliability performance in industry standard test conditions. Besides, this paper will also present a study of package level warpage behaviour with Thermo-Moire measurement.

Enabling Packaging Houses to Achieve 3D Integration without Interposers

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000893-000923
Author(s):  
Jeff Leal ◽  
Marc Robinson ◽  
Suzette Pangrle
Keyword(s):  
Current System ◽  
3D Structure ◽  
Consumer Electronics ◽  
Temperature Cycle ◽  
3D Integration ◽  
Novel Method ◽  
System Requirements ◽  
Traditional Approaches ◽  
Electrical Connections ◽  
Temperature Storage

The growth of small portable consumer electronics has increased the requirements of creating densely stacked packages with ever decreasing footprints while still increasing storage capacities as well as accessible memory. Traditional approaches to create these packages have included wire-bonding and Package on Package (PoP) as well as through Silicon Via (TSV). All of these methods present a solution to current system requirements, each with its own drawback. This paper will discuss a novel method in which a vertical 3D die stack can be created of similar an in some cases dissimilar die. The final 3D structure of stacked die will present no XY offset between any level of the die stack achieving the smallest possible form factor. This method also eliminates the requirements of creating an interposer for the electrical connection between layers. The final result is a completely vertical die stack with electrical connections drawn on the outside edges of the die stack which adds <400um total in either the X or Y axis of the package. We will discuss required equipment, the best known methods and the optimal materials required to achieve the final product as well as JEDEC reliability data proving package robustness, such as Temperature Cycle, biased-HAST and High Temperature Storage.

Design and Direct Assembly of 2.5D/3D Rigid Silicon Interposer on PCB

2014 ◽  
Vol 2014 (1) ◽  
pp. 000783-000786 ◽  
Author(s):  
Farhang Yazdani
Keyword(s):  
Flip Chip ◽  
Thermal Stresses ◽  
Stress Test ◽  
Temperature Cycle ◽  
3D Integration ◽  
Test Vehicle ◽  
Direct Assembly ◽  
Solder Balls ◽  
Present Design ◽  
The Cost

Silicon interposer is emerging as a vehicle for integrating dies with sub 50um bump pitch in 2.5D/3D configuration. Benefits of 2.5D/3D integration are well explained in the literature, however, cost and reliability is a major concern especially with the increase in interposer size. Among the challenges, reliability issues such as warpage, cracks and thermal-stresses must be managed, in addition, multi-layer build-up flip chip substrate cost and its impact on the overall yield must be considered. Because of these challenges, 2.5D/3D silicon interposer has developed a reputation as a costly process. To overcome the reliability challenges and cost associated with typical thin interposer manufacturing and assembly, a rigid silicon interposer type structure is disclosed. In this study, interposer with thickness of greater than 300um is referred to as rigid interposer. Rigid silicon interposer is directly assembled on PCB without the need for intermediary substrate. This eliminates the need for an intermediary substrate, thin wafer handling, wafer bonding/debonding procedures and Through Silicon Via (TSV) reveal processes, thus, substantially reducing the cost of 2.5D/3D integrated products while improving reliability. A 10X10mm2 rigid silicon interposer test vehicle with 310um thickness was designed and fabricated. BGA side of the interposer with 1mm ball pitch was bumped with eutectic solder balls through a reflow process. Interposer was then assembled on a 50X50mm2 FR-4 PCB. We present design and direct assembly of the rigid silicon interposer on PCB followed by temperature cycle results using CSAM images at 250, 500, 750 and 1000 cycles. It is shown that all samples successfully passed the temperature cycle stress test.

Package Thickness - Ultrathin WLFO (Wafer-Level Fan-Out)

2016 ◽  
Vol 2016 (1) ◽  
pp. 000305-000308
Author(s):  
Eoin O'Toole ◽  
Steffen Kroehnert ◽  
José Campos ◽  
Virgilio Barbosa ◽  
Leonor Dias
Keyword(s):  
System Integration ◽  
Dimensional Space ◽  
Three Dimensional ◽  
Battery Life ◽  
Wafer Level ◽  
Display Area ◽  
Solder Balls ◽  
Bga Package ◽  
Wafer Processing ◽  
Semiconductor Packages

Abstract NANIUM's Fan-Out Wafer-Level Packaging technology WLFO (Wafer-Level Fan-Out) is based on embedded Wafer-Level Ball Grid Array technology eWLB of Infineon Technologies [1]. Since it′s invention almost 10 years ago, it became the leading technology for Fan-Out Wafer-Level packages. The WLFO technology is based upon the reconstitution of KGD (known good die) from incoming device wafer, independent of wafer diameter and material, to recon wafer format of active semiconductor dies or other active/passive components separated by mold compound applied through compression molding on a temporary mold carrier. The resulting recon wafer can be processed in standard wafer processing equipment. One of the challenges for the future of semiconductor packaging is reduction of the board level volume real estate occupied by each component. With the drive towards lower profile end user devices incorporating large display area and battery life the three dimensional space available for semiconductor packages is diminishing. It is well known that WLFO single die packaging but even more significant system integration enables the shrinkage of the XY footprint of the package through flexible very dense heterogeneous system-in-package integration [2]. But one of the disruptive advantages of the substrate-less WLFO technology is to also permit significant reduction of the overall package height (Z). A total package height for a BGA package including solder balls <500um and for a LGA package with solder land pads only <300um is achievable today, and further development towards even thinner packages is on the way.

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