Development of Lead-Free Flip Chip Package and Its Reliability

2003 ◽  
Author(s):  
Jeffrey C. B. Lee ◽  
Sting Wu ◽  
H. L. Chou ◽  
Yi-Shao Lai
Keyword(s):  
Failure Mode ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Wire Bonding ◽  
Point Of View ◽  
Lead Free ◽  
Temperature Cycle ◽  
Snagcu Solder ◽  
Temperature Cycle Test

SnAgCu solder used in laminate package like PBGA and CSP BGA to replace eutectic SnPb as interconnection has become major trend in the electronic industry. But unlike well-known failure mode of wire bonding package, flip chip package with SnAgCu inner solder bump and external solder ball as electrical interconnection present a extremely different failure mode with wire-bonding package from a point of view in material and process. In this study, one 16mm×16mm 3000 I/O SnAgCu wafer bumping using screen-printing process was explored including the effects of reflow times, high temperature storage life (HTSL) and temperature cycle test (TCT) on bump shear strength. Furthermore, the qualified wafer bumping is assembled by flip chip assembly with various underfill material and specific organic build-up substrate, then is subject to MSL4/260°C precondition and temperature cycle test to observe the underfill effect on SnAgCu bump protection and solder joint life. Various failure modes in the flip chip package like solder bump, underfill and UBM and so on, will be scrutinized with SEM. And finally, best material combination will be addressed to make the lead free flip package successful.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Maskless Process for Fabrication of Ultra-Fine Pitch Solder Bumps for Flip Chip Interconnects

2003 ◽  
Vol 125 (4) ◽  
pp. 597-601
Author(s):  
R. T. P. Lee ◽  
A. S. Zuruzi ◽  
S. K. Lahiri
Keyword(s):  
Failure Mode ◽  
Flip Chip ◽  
Solder Bump ◽  
Low Cost ◽  
High Stress ◽  
Lead Free ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Dimensional Uniformity ◽  
Lift Off

The results of this study demonstrate the viability of a low cost maskless process for the fabrication of ultra-fine pitch solder bumps. The fabricated solder bump arrays have a pitch and diameter of 120 and 70 μm, respectively. Widely used eutectic 63Sn37Pb and lead-free 95.5Sn3.8Ag0.7Cu solders were used to form the bumps. No solder bridging was observed between adjacent bumps, and the solder bumps exhibited good dimensional uniformity. The solder bump to aluminum (Al) pad bond integrity was found to be excellent, as evidenced by the high stress to failure. The failure mode is predominately Al pad lift-off indicating a robust solder bump-pad joint.

Ultralow Residue (ULR) Semiconductor Grade Fluxes for Flip-Chip and MEMs Applications

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001475-001501
Author(s):  
Maria Durham ◽  
SzePei Lim ◽  
Jason Chou ◽  
Andy Mackie
Keyword(s):  
Failure Mode ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Yield Loss ◽  
Joint Damage ◽  
Jet Impingement ◽  
Pillar Height

Copper pillars topped with solder microbumps are emerging as a standard flip-chip solder bump replacement in the semiconductor assembly industry. The relentless drive towards finer pitch, combined with reduced copper pillar height, makes aqueous cleaning of flip-chip flux residues more difficult. An emergent failure mode is joint damage and subsequent yield loss during aqueous jet impingement. The move towards semiconductor grade ultralow residue no-clean fluxes and away from cleaning processes is therefore inevitable for both flip-chip and MEMS applications to meet industry roadmap challenges. The low residue also optimizes underfill adhesion and decreases possible outgassing during underfill cure. This paper discusses the variety of new and emerging failure modes for new packing processes using thinned die with copper-pillar/microbumps. The testing of assembly materials for this purpose will also be discussed.

Practical Application and Analysis of Lead-Free Solder on Chip-On-Flip-Chip SiP for Hearing Aids

2017 ◽  
Vol 2017 (1) ◽  
pp. 000201-000207 ◽  
Author(s):  
Youngtak Lee ◽  
Doug Link
Keyword(s):  
Hearing Aids ◽  
Flip Chip ◽  
Failure Modes ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Practical Application ◽  
Surface Mount ◽  
Free Solder ◽  
On Chip

Abstract Due to rapid growth of the microelectronics industry, packaged devices with small form factors, low costs, high power performance, and increased efficiency have become of high demand in the market. To realize the current market development trend, flip chip interconnection and System-in-Package (SiP) are some of the promising packaging solutions developed. However, a surprising amount of surface mount technology (SMT) defects are associated with the use of lead-free solder paste and methods by which the paste is applied. Two such defects are solder extrusion and tombstoning. Considerable amount of defects associated with solder overflow are found on chip-on-flip-chip (COFC) SiP in hearing aids. Through the use of design of experiments (DOE), lead-free solder defect causes on hearing aids application can be better understood and subsequently reduced or eliminated. This paper will examine the failure modes of solder extrusion and tombstoning that occurred when two different types of lead-free solders, Sn-Ag-Cu (SAC) and BiAgX were used within a SiP for attachment of surface mount devices (SMD) chip components for hearing aid applications. The practical application and analysis of lead-free solder for hearing aids will include the comprehensive failure analysis of the SMD components and compare the modeling and analysis of the two different solder types through the DOE process.

Comparative Modeling and Analysis of Lead-Free Solder Extrusion for the Design of Reliability

2016 ◽  
Vol 2016 (1) ◽  
pp. 000111-000116
Author(s):  
Youngtak Lee ◽  
Doug Link
Keyword(s):  
Design Of Experiments ◽  
Flip Chip ◽  
Failure Modes ◽  
Form Factors ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Modeling And Analysis ◽  
Surface Mount ◽  
Free Solder

Abstract Due to rapid growth of the microelectronics industry, packaged devices with small form factors, low costs, high power performance, and increased efficiency have become of high demand in the market. To realize the current market development trend, flip chip interconnection and System-in-Package (SiP) are some of the promising packaging solutions developed. However, a surprising amount of surface mount technology (SMT) defects are associated with the use of lead-free solder paste and methods by which the paste is applied. Two such defects are solder extrusion and tombstoning. Through the use of design of experiments (DOE), lead-free solder defect causes can be better understood and subsequently reduced or eliminated. This paper will examine the failure modes of solder extrusion and tombstoning that occurred when two different types of lead-free solders, Sn-Ag-Cu (SAC) and BiAgX were used within a SiP for attachment of surface mount devices (SMD) chip components. The systematic investigation will include the comprehensive failure analysis of the SMD components and compare the modeling and analysis of the two different solder types utilizing the design of experiments methods.

Thermally Activated Bumping Process using Sn3.0Ag0.5Cu Solder Powder for Low-Cost Interposers

2013 ◽  
Vol 2013 (1) ◽  
pp. 000420-000423
Author(s):  
Kwang-Seong Choi ◽  
Ho-Eun Bae ◽  
Haksun Lee ◽  
Hyun-Cheol Bae ◽  
Yong-Sung Eom
Keyword(s):  
Screen Printing ◽  
Flip Chip ◽  
Solder Bump ◽  
Low Cost ◽  
Organic Substrate ◽  
Lead Free ◽  
Lead Free Solder ◽  
Thermally Activated ◽  
Fine Pitch ◽  
Free Solder

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.

Underfill Assessments and Validations for Low-k FCBGA

2006 ◽  
Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Performance ◽  
Low K ◽  
Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

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