Hermetically Sealed Glass Packages

Significant advances have been accomplished in the field of Through Glass Via (TGV) technology; enabling a new generation of electronic designs that achieve higher performance, while leveraging low cost system solutions. Through-hole creation methods in glass have been optimized for mass production with consistent via diameter, shape and wall chemistry/morphology. This has enabled the development of unique copper via metallization materials that exhibit very high conductivity, thermal expansion matching (with borosilicate glass) and hermeticity in the 10E-10 Atm.cc/sec range (Ultra-High Vacuum Hermeticity). Further developments in Chemical Mechanical Polishing (CMP) for glass wafers with copper vias, surface sensitization and metal deposition techniques, have enabled thin film metallization on both sides of the glass wafer for fine line redistribution layers (RDL). The thin film RDL is compatible with the TGV with excellent continuity in conductivity. The RDL metallization is plated to allow flip chip, land grid array, wire-bond, solder, or other interconnection methods. The paper will discuss the technical, material and process challenges in each of the areas mentioned above which enable a hermetically sealed glass package. Detailed data and experimental results will be discussed.

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RDL Multilayer Metallization Approaches for TGV

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2017dpc-ta1_presentation3 ◽

2017 ◽

Vol 2017 (DPC) ◽

pp. 1-11 ◽

Cited By ~ 1

Author(s):

Roupen Keusseyan ◽

Tim Mobley ◽

Elizabeth Young-Dohe

Keyword(s):

Dielectric Material ◽

Low Cost ◽

Electrical Contact ◽

Glass Wafer ◽

Adhesion Layer ◽

Cost System ◽

Expansion Matching ◽

New Generation ◽

Multilayer Metallization ◽

Unique Chemical

Significant advances have been accomplished in the field of Through Glass Via (TGV) technology; enabling a new generation of electronic designs that achieve higher performance, while leveraging low cost system solutions. Through-hole creation methods in glass have been optimized for mass production with consistent via diameter, shape and wall chemistry/morphology. This has enabled the development of unique copper via metallization materials that exhibit very high conductivity, thermal expansion matching and hermeticity. This paper will discuss post via metallization processes for multilayer RDL (Redistribution Layer) metallization on both sides of the glass wafer. Unique Chemical Mechanical Polishing (CMP) development approaches for glass wafers with copper thick film vias will be explained. Thin film deposited adhesion layer on glass, followed by a deposited metallization layer will be described. Types of deposited adhesion layer on glass for optimized adhesion and electrical contact with the vias will be examined. Furthermore, copper plating approaches for higher conductivity and fine line circuit patterning are examined. Polymeric dielectric material systems for multilayer RDL on both sides of the glass will also be reviewed.

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Characterization of a Semiconductor Packaging System utilizing Through Glass Via (TGV) Technology

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2015dpc-wp13 ◽

2015 ◽

Vol 2015 (DPC) ◽

pp. 001378-001407

Author(s):

Tim Mobley ◽

Roupen Keusseyan ◽

Tim LeClair ◽

Konstantin Yamnitskiy ◽

Regi Nocon

Keyword(s):

Low Cost ◽

Glass Wafer ◽

Wafer Level ◽

Packaging System ◽

Thin Glass ◽

Wafer Level Packaging ◽

Recent Developments ◽

And Performance ◽

New Generation ◽

Semiconductor Packaging

Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging. This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specifications required for through glass vias (TGV's). Creating redistribution layers (RDL) or circuit layers on both sides of large thin glass wafer poses several challenges, which this paper will discuss, as well as, performance and reliability of the circuit layers on TGV wafers or substrates. Additionally, there are glass-to-glass welding techniques that can be utilized in conjunction with TGV wafers with RDL, which provide ambient glass-to-glass attachments of lids and standoffs, which do not outgas during thermal cycle and allow the semiconductor devices to be attached first without having to reflow at lower temperatures. Fabrication challenges, reliability testing results, and performance of this semiconductor packaging system will be discussed in this paper.

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Some applications of a torsion microbalance for the investigation of surface phenomena and thin film properties in ultra-high vacuum

Vacuum ◽

10.1016/0042-207x(64)91130-3 ◽

1964 ◽

Vol 14 (4) ◽

pp. 166

Keyword(s):

Thin Film ◽

High Vacuum ◽

Ultra High Vacuum ◽

Surface Phenomena ◽

Film Properties

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Analysis of a Non-Evaporable Getter of Ti-Al-Zr Thin Film with Enhanced Performance Used for Ultra-High Vacuum Generation

Journal of the Korean Physical Society ◽

10.3938/jkps.75.373 ◽

2019 ◽

Vol 75 (5) ◽

pp. 373-379

Author(s):

Muhammad Khalid Alamgir ◽

M. Ikram ◽

Ghalib Hussain Mughal ◽

Ghulam Asghar ◽

Shafiq ur Rehman ◽

...

Keyword(s):

Thin Film ◽

High Vacuum ◽

Ultra High Vacuum ◽

Vacuum Generation

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Precise nanoscale temperature mapping in operational microelectronic devices by use of a phase change material

Scientific Reports ◽

10.1038/s41598-020-77021-1 ◽

2020 ◽

Vol 10 (1) ◽

Author(s):

Qilong Cheng ◽

Sukumar Rajauria ◽

Erhard Schreck ◽

Robert Smith ◽

Na Wang ◽

...

Keyword(s):

Thin Film ◽

Phase Change ◽

Phase Change Material ◽

Heat Dissipation ◽

Radiation Thermometry ◽

High Vacuum ◽

Operating Conditions ◽

Ultra High Vacuum ◽

Scanning Thermal Microscopy ◽

Change Material

AbstractThe microelectronics industry is pushing the fundamental limit on the physical size of individual elements to produce faster and more powerful integrated chips. These chips have nanoscale features that dissipate power resulting in nanoscale hotspots leading to device failures. To understand the reliability impact of the hotspots, the device needs to be tested under the actual operating conditions. Therefore, the development of high-resolution thermometry techniques is required to understand the heat dissipation processes during the device operation. Recently, several thermometry techniques have been proposed, such as radiation thermometry, thermocouple based contact thermometry, scanning thermal microscopy, scanning transmission electron microscopy and transition based threshold thermometers. However, most of these techniques have limitations including the need for extensive calibration, perturbation of the actual device temperature, low throughput, and the use of ultra-high vacuum. Here, we present a facile technique, which uses a thin film contact thermometer based on the phase change material $$Ge_2 Sb_2 Te_5$$ G e 2 S b 2 T e 5 , to precisely map thermal contours from the nanoscale to the microscale. $$Ge_2 Sb_2 Te_5$$ G e 2 S b 2 T e 5 undergoes a crystalline transition at $$\hbox {T}_{{g}}$$ T g with large changes in its electric conductivity, optical reflectivity and density. Using this approach, we map the surface temperature of a nanowire and an embedded micro-heater on the same chip where the scales of the temperature contours differ by three orders of magnitude. The spatial resolution can be as high as 20 nanometers thanks to the continuous nature of the thin film.

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