Accurate and Low-cost Scheme for Network Path Delay Measurement

2013 ◽  
Vol 8 (6) ◽  
Author(s):  
Shiqiang Chen ◽  
Junfeng Wang ◽  
Yifang Qin ◽  
Xu Zhou
2019 ◽  
Vol 28 (09) ◽  
pp. 1950149
Author(s):  
Bahram Rashidi ◽  
Mohammad Abedini

This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of [Formula: see text] and [Formula: see text] for general and special cases of BECs, respectively, where [Formula: see text] and [Formula: see text] denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields [Formula: see text] and [Formula: see text] are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.


Author(s):  
Neelufar Naheed Saudagar ◽  
◽  
Seema Deshmukh

2020 ◽  
Vol 2020 ◽  
pp. 1-13
Author(s):  
Mohd Tausif ◽  
Ekram Khan ◽  
Mohd Hasan ◽  
Martin Reisslein

This paper proposes and evaluates the LFrWF, a novel lifting-based architecture to compute the discrete wavelet transform (DWT) of images using the fractional wavelet filter (FrWF). In order to reduce the memory requirement of the proposed architecture, only one image line is read into a buffer at a time. Aside from an LFrWF version with multipliers, i.e., the LFr WF m , we develop a multiplier-less LFrWF version, i.e., the LFr WF ml , which reduces the critical path delay (CPD) to the delay T a of an adder. The proposed LFr WF m and LFr WF ml architectures are compared in terms of the required adders, multipliers, memory, and critical path delay with state-of-the-art DWT architectures. Moreover, the proposed LFr WF m and LFr WF ml architectures, along with the state-of-the-art FrWF architectures (with multipliers (Fr WF m ) and without multipliers (Fr WF ml )) are compared through implementation on the same FPGA board. The LFr WF m requires 22% less look-up tables (LUT), 34% less flip-flops (FF), and 50% less compute cycles (CC) and consumes 65% less energy than the Fr WF m . Also, the proposed LFr WF ml architecture requires 50% less CC and consumes 43% less energy than the Fr WF ml . Thus, the proposed LFr WF m and LFr WF ml architectures appear suitable for computing the DWT of images on wearable sensors.


2021 ◽  
Vol 13 (16) ◽  
pp. 3285
Author(s):  
Yongqian Chen ◽  
Songhua Yan ◽  
Jianya Gong

Deformation monitoring has been brought to the fore and extensively studied in recent years. Global Navigation Satellite System Reflectometry (GNSS-R) techniques have so far been developed in deformation estimation applications, which however, are subject to the influence of mobile satellites. Rather than compensating for the path delay variations caused by mobile satellites, adopting Beidou geostationary Earth orbit (GEO) satellites as transmitters directly eliminates the satellite-motion-induced phase error and thus provides access to stable phase information. This paper presents a novel deformation monitoring concept based on GNSS-R utilizing Beidou GEO satellites. The geometrical properties of the GEO-based bistatic GNSS radar system are explored to build a theoretical connection between deformation quantity and the echo carrier phases. A deformation retrieval algorithm is proposed based on the supporting software receiver, thus allowing echo carrier phases to be extracted and utilized in deformation retrieval. Two field validation experiments are conducted by constructing passive bistatic radars with reflecting plates and ground receiver. Utilizing the proposed algorithm, the experimental results suggested that the GEO-based GNSS reflectometry can achieve deformation estimations with an accuracy of around 1 cm when the extracted phases does not exceed one complete cycle, while better than 3 cm when considering the correct integer number of phase cycles. Consequently, based on the passive bistatic radar system, the potential of achieving continuous, low-cost deformation monitoring makes this novel technique noteworthy.


2014 ◽  
pp. 8-14
Author(s):  
Vladimir Haasz ◽  
Jaroslav Roztocil ◽  
Jan Breuer ◽  
Vojtěch Vigner

Nowadays there is a frequent demand to increase the quality of synchronization in industrial distributed systems. Node synchronization can be implemented in the Ethernet network using time protocols, e.g. IEEE 1588 Precise Time Protocol (PTP). However, active network components like switches and routers have negative influence on achieved accuracy of synchronization because they affect a packet delay variation in the network. To suppress this effect, special (but expensive) industrial switches, with a packet propagation delay correction, can be used. Another way using either low cost GPS receivers for synchronization of local clocks or a special timing for data transfer is described in the paper. It will allow a cheaper solution that preserves high quality of synchronization. Besides, a device for packet delay measurement (PTP tester) was designed and developed to be possible to evaluate the proposed methods.


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