Building custom hardware tools

2021 ◽  
pp. 193-203
Author(s):  
Kirsten Hermes
Keyword(s):  
Custom Hardware

scholarly journals Development of Non Expensive Technologies for Precise Maneuvering of Completely Autonomous Unmanned Aerial Vehicles

Sensors ◽  
2021 ◽  
Vol 21 (2) ◽  
pp. 391
Author(s):  
Luca Bigazzi ◽  
Stefano Gherardini ◽  
Giacomo Innocenti ◽  
Michele Basso
Keyword(s):  
Unmanned Aerial Vehicles ◽  
Degrees Of Freedom ◽  
Vision System ◽  
Video Stream ◽  
Measurement Unit ◽  
Absolute Position ◽  
Light Load ◽  
Aerial Vehicles ◽  
Angular Velocities ◽  
Custom Hardware

In this paper, solutions for precise maneuvering of an autonomous small (e.g., 350-class) Unmanned Aerial Vehicles (UAVs) are designed and implemented from smart modifications of non expensive mass market technologies. The considered class of vehicles suffers from light load, and, therefore, only a limited amount of sensors and computing devices can be installed on-board. Then, to make the prototype capable of moving autonomously along a fixed trajectory, a “cyber-pilot”, able on demand to replace the human operator, has been implemented on an embedded control board. This cyber-pilot overrides the commands thanks to a custom hardware signal mixer. The drone is able to localize itself in the environment without ground assistance by using a camera possibly mounted on a 3 Degrees Of Freedom (DOF) gimbal suspension. A computer vision system elaborates the video stream pointing out land markers with known absolute position and orientation. This information is fused with accelerations from a 6-DOF Inertial Measurement Unit (IMU) to generate a “virtual sensor” which provides refined estimates of the pose, the absolute position, the speed and the angular velocities of the drone. Due to the importance of this sensor, several fusion strategies have been investigated. The resulting data are, finally, fed to a control algorithm featuring a number of uncoupled digital PID controllers which work to bring to zero the displacement from the desired trajectory.

Custom hardware support for realtime ray tracing

2005 ◽  
Author(s):  
Philipp Slusallek ◽  
Peter Shirley ◽  
William Mark ◽  
Gordon Stoll ◽  
Ingo Wald
Keyword(s):  
Ray Tracing ◽  
Hardware Support ◽  
Custom Hardware

Multithreaded Programming of Reconfigurable Embedded Systems

2011 ◽  
pp. 31-54
Author(s):  
Jason Agron ◽  
David Andrews ◽  
Markus Happe ◽  
Enno Lübbers ◽  
Marco Platzner
Keyword(s):  
Development Time ◽  
Programming Model ◽  
General Purpose ◽  
System Level ◽  
Performance Ratio ◽  
Multithreaded Programming ◽  
Price Performance ◽  
Flexible Hardware ◽  
Custom Hardware ◽  
Application Requirements

Embedded and Real-Time (ERTS) systems have continued to expand at a vigorous rate. Designers of ERTS systems are continually challenged to provide new capabilities that can meet the expanding requirements and increased computational needs of each new proposed application, but at a decreasing price/performance ratio. Conventional solutions using general purpose processors or custom ASICs are less and less able to satisfy the contradictory requirements in performance, flexibility, power, development time, and cost. This chapter introduces the concept of generating semi-custom platforms driven from a traditional multithreaded programming model. This approach offers the advantage of achieving productivity levels close to those associated with software by using an established programming model but with a performance level close to custom hardware through the use of a flexible hardware platform capable of adapting to specialized application requirements. We discuss the underlying concepts, requirements and advantages of multithreading in the context of reconfigurable hardware, and present two approaches which provide multithreading support to hardware and software components at the operating system level.

scholarly journals Automatic Tool for Fast Generation of Custom Convolutional Neural Networks Accelerators for FPGA

Electronics ◽  
2019 ◽  
Vol 8 (6) ◽  
pp. 641 ◽  
Author(s):  
Miguel Rivera-Acosta ◽  
Susana Ortega-Cisneros ◽  
Jorge Rivera
Keyword(s):  
Neural Networks ◽  
Convolutional Neural Networks ◽  
State Of The Art ◽  
Register Transfer Level ◽  
Third Party ◽  
Hardware Accelerators ◽  
Field Programmable ◽  
Custom Hardware ◽  
Architecture Description ◽  
Automatic Tool

This paper presents a platform that automatically generates custom hardware accelerators for convolutional neural networks (CNNs) implemented in field-programmable gate array (FPGA) devices. It includes a user interface for configuring and managing these accelerators. The herein-presented platform can perform all the processes necessary to design and test CNN accelerators from the CNN architecture description at both layer and internal parameter levels, training the desired architecture with any dataset and generating the configuration files required by the platform. With these files, it can synthesize the register-transfer level (RTL) and program the customized CNN accelerator into the FPGA device for testing, making it possible to generate custom CNN accelerators quickly and easily. All processes save the CNN architecture description are fully automatized and carried out by the platform, which manages third-party software to train the CNN and synthesize and program the generated RTL. The platform has been tested with the implementation of some of the CNN architectures found in the state-of-the-art for freely available datasets such as MNIST, CIFAR-10, and STL-10.

scholarly journals Accurate Sampling with Noisy Forces from Approximate Computing

Computation ◽  
2020 ◽  
Vol 8 (2) ◽  
pp. 39 ◽  
Author(s):  
Varadarajan Rengaraj ◽  
Michael Lass ◽  
Christian Plessl ◽  
Thomas D. Kühne
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Computer Simulations ◽  
High Efficiency ◽  
Type Equation ◽  
Low Power Consumption ◽  
Approximate Computing ◽  
Expectation Values ◽  
Computing Paradigm ◽  
Custom Hardware

In scientific computing, the acceleration of atomistic computer simulations by means of custom hardware is finding ever-growing application. A major limitation, however, is that the high efficiency in terms of performance and low power consumption entails the massive usage of low precision computing units. Here, based on the approximate computing paradigm, we present an algorithmic method to compensate for numerical inaccuracies due to low accuracy arithmetic operations rigorously, yet still obtaining exact expectation values using a properly modified Langevin-type equation.

Establishing Computer-Access Centers: Challenge for the ‘80s

1984 ◽  
Vol 78 (9) ◽  
pp. 435-436 ◽  
Author(s):  
Jeffrey J. Moyer
Keyword(s):  
Service Delivery ◽  
Visually Impaired ◽  
New Technologies ◽  
Visual Impairments ◽  
Delivery Systems ◽  
Computer Access ◽  
Service Delivery Systems ◽  
Custom Hardware ◽  
Made In

While great advances have been made in custom hardware and software which make computers accessible to individuals with severe visual impairments, service delivery systems have not kept pace with the technology. A range of new services needs to be established through computer-access centers if visually impaired individuals are to realize the full benefits of the new technologies.

A Primer for Telemetry Interfacing in Accordance with NASA Standards Using Low Cost FPGAs

2016 ◽  
Vol 05 (01) ◽  
pp. 1640002
Author(s):  
Jake McCoy ◽  
Ted Schultz ◽  
James Tutt ◽  
Thomas Rogers ◽  
Drew Miles ◽  
...  
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Photon Counting ◽  
Sounding Rocket ◽  
Photon Counting Detector ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Custom Hardware ◽  
Commercial Off The Shelf ◽  
Main Component

Photon counting detector systems on sounding rocket payloads often require interfacing asynchronous outputs with a synchronously clocked telemetry (TM) stream. Though this can be handled with an on-board computer, there are several low cost alternatives including custom hardware, microcontrollers and field-programmable gate arrays (FPGAs). This paper outlines how a TM interface (TMIF) for detectors on a sounding rocket with asynchronous parallel digital output can be implemented using low cost FPGAs and minimal custom hardware. Low power consumption and high speed FPGAs are available as commercial off-the-shelf (COTS) products and can be used to develop the main component of the TMIF. Then, only a small amount of additional hardware is required for signal buffering and level translating. This paper also discusses how this system can be tested with a simulated TM chain in the small laboratory setting using FPGAs and COTS specialized data acquisition products.

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