scholarly journals Power Consumption Improvements in AES Decryption Based on Null Convention Logic

2021 ◽  
Vol 15 ◽  
pp. 254-264
Author(s):  
Toi Le Thanh ◽  
Lac Truong Tri ◽  
Hoang Trang
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
Circuit Design ◽  
Design Method ◽  
Circuit Model ◽  
Maximum Speed ◽  
Test Model ◽  
Asynchronous Circuit ◽  
Design Models ◽  
Null Convention Logic

In this paper, we propose a new asynchronous method based on a Null Convention Logic (NCL) to improve power consumption for low power integrated circuits. The reason is because the NCL based designs do not use a clock, it eliminates the problems related to the clock and its power consumption reduces significantly. To show the advantages of the selected method, we propose two design models using the synchronous circuit design method, and the NCL based asynchronous circuit design method. To test these two design models conveniently, we also propose an extra automatic test model. In this study, the AES decryption is used as an example to illustrate both methods. The two above proposed AES decryption models are simulated and synthesized at the various corners by VCS and Design Compiler tool using TSMC standard cell libraries in 65nm technology. The synthesis results of the two above mentioned models indicated that the power consumption of the NCL based asynchronous circuit model is 3 times lower than that of the synchronous circuit model, and significantly improves (from 94% to 98%) compared with the results of the other authors. The processing speed of the NCL based asynchronous circuit paradigm is able to achieve a maximum speed.

The Micro Fluidic Integrated Circuits Design Method based on the CAD System

2011 ◽  
Vol 66-68 ◽  
pp. 1930-1935 ◽  
Author(s):  
San Ping Zhao
Keyword(s):  
Integrated Circuits ◽  
Circuit Design ◽  
Design Method ◽  
Cad System ◽  
Spice Model ◽  
Fluidic Circuits ◽  
First Time

In this study, SPICE program is applied to design micro fluidic circuits based on the analogical relationship with MOSFET models for the first time. A SPICE model of pneumatic-FET is established to express the behavior of them in micro fluidic circuits. Construction of pneumatic-FET model, its optimization, and effectiveness in circuit design and comparison are discussed in the later sections.

scholarly journals Low power circuit design using NCL based asynchronous method

2021 ◽  
Vol 22 (3) ◽  
pp. 1284
Author(s):  
Toi Le Thanh ◽  
Lac Truong Tri ◽  
Trang Hoang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Electromagnetic Interference ◽  
Design Model ◽  
Design Technique ◽  
Asynchronous Circuit ◽  
Clock Gating ◽  
Power Circuit ◽  
Asynchronous Circuit Design

The null convention logic (NCL) based circuit design methodology eliminates the problems related to noise, clock tree, electromagnetic interference and also reduces significant power consumption. In this paper, we would like to demonstrate the advantage of low power consumption of the NCL based asynchronous circuit design on a large design scale, thus we used the advanced encryption standard (AES) encryption design as an illustrative example. In addition, we also proposed two pipelined AES encryption models using the synchronous circuit design technique and the asynchronous circuit design technique based on NCL. Besides, these two models were realized by using version control system (VCS) tool to simulate and Design Compiler tool to synthesize parameters in power consumption, processing speed and area. The synthesis results of these two models indicated that power consumption of the NCL based asynchronous AES encryption model had a decrease of 71% compared with the synchronous AES encryption model. Moreover, we show the outstanding advantage of the power consumption of the NCL based asynchronous design model (a decrease of 91.12% and 93,23%) compared to the synchronous design model using clock gating technique and without using clock gating technique respectively.

scholarly journals Designing ALU using GDI method

2019 ◽  
Vol 8 (3) ◽  
pp. 151
Author(s):  
Mohammadreza Fadaei
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Low Power Consumption ◽  
Ic Design ◽  
Advantages And Disadvantages ◽  
Circuit Resistance

<p>As CMOS technology is continuously becoming smaller and smaller in nanoscale regimes, and circuit resistance to changes in the process for the design of the circuit is a major obstacle. Storage elements such as memory and flip-flops are particularly vulnerable to the change process. Power consumption is also another challenge in today's Digital IC Design. In modern processors, there are a large number of transistors, more than a billion transistors, which increases the temperature and the breakdown of its performance. Therefore, circuit design with low power consumption is a critical need for integrated circuits today. In this study, we deal with GDI techniques for designing logic and arithmetic circuits. We show that this logic in addition to low power consumption has little complexity so that arithmetic and logic circuits can be implemented with fewer transistors. Various circuits such as adders, differentiation and multiplexers, etc. have been designed and implemented using these techniques, and published in various articles. In this study, we review and evaluate the advantages and disadvantages of these circuits.</p>

A CMOS combinational circuit-design method using mixed logic concepts

1995 ◽  
Vol 38 (3) ◽  
pp. 266-273 ◽  
Author(s):  
W.B. Hudson ◽  
J.S. Beasley ◽  
J.E. Steelman
Keyword(s):  
Circuit Design ◽  
Design Method ◽  
Combinational Circuit
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