scholarly journals Revisiting the functional bootstrap in TFHE

2021 ◽  
pp. 229-253
Author(s):  
Antonio Guimarães ◽  
Edson Borin ◽  
Diego F. Aranha
Keyword(s):  
High Precision ◽  
Arbitrary Function ◽  
Error Propagation ◽  
Logic Gates ◽  
Error Variance ◽  
Previous Literature ◽  
Lookup Table ◽  
Table Lookup ◽  
Bootstrap Procedure

The FHEW cryptosystem introduced the idea that an arbitrary function can be evaluated within the bootstrap procedure as a table lookup. The faster bootstraps of TFHE strengthened this approach, which was later named Functional Bootstrap (Boura et al., CSCML’19). From then on, little effort has been made towards defining efficient ways of using it to implement functions with high precision. In this paper, we introduce two methods to combine multiple functional bootstraps to accelerate the evaluation of reasonably large look-up tables and highly precise functions. We thoroughly analyze and experimentally validate the error propagation in both methods, as well as in the functional bootstrap itself. We leverage the multi-value bootstrap of Carpov et al. (CT-RSA’19) to accelerate (single) lookup table evaluation, and we improve it by lowering the complexity of its error variance growth from quadratic to linear in the value of the output base. Compared to previous literature using TFHE’s functional bootstrap, our methods are up to 2.49 times faster than the lookup table evaluation of Carpov et al. (CT-RSA’19) and up to 3.19 times faster than the 32-bit integer comparison of Bourse et al. (CT-RSA’20). Compared to works using logic gates, we achieved speedups of up to 6.98, 8.74, and 3.55 times over 8-bit implementations of the functions ReLU, Addition, and Maximum, respectively.

The Design and Implementation of High Precision Three-Phase Sine-Wave Signal Generator

2014 ◽  
Vol 543-547 ◽  
pp. 838-841
Author(s):  
Shou Qiang Kang ◽  
Shan Shan Li ◽  
Shi Zheng ◽  
Di Wu
Keyword(s):  
High Precision ◽  
Design Method ◽  
Synthesis Method ◽  
Sine Wave ◽  
Signal Generator ◽  
Lookup Table ◽  
Direct Digital Frequency Synthesis ◽  
Wave Signal ◽  
Design And Implementation ◽  
Three Phase

A design and implementation method of high precision three-phase sine-wave signal generator is proposed based on MCU and FPGA. For the traditional design method, direct analog synthesis method and phase locked loop (PLL) technology are used to design the signal generator. So the function, the precision and other aspects are inadequate. Aiming to the problem, a signal generator is designed based on direct digital frequency synthesis (DDS) technology. The MCU is used to control the peripheral devices and the frequency and phase control word can be obtained. The DDS module is achieved by EP4CE6E22C8 and the waveform lookup table addresses are outputted. The digital three-phase sine-wave data can be read from the lookup table. Through the three-way D/A converter and the amplifier circuit, the digital signal is converted to analog signal and the three-phase sinusoidal wave is outputted. The precision can be improved by increasing the sampling points, phase accumulator bits and D/A bits, and then, high precision three-phase sine-signal can be obtained and the adjustable frequency precision is 0.001.

scholarly journals Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Salah Hasan Ibrahim ◽  
Sawal Hamid Md. Ali ◽  
Md. Shabiul Islam
Keyword(s):  
High Speed ◽  
Frequency Synthesizer ◽  
Logic Gates ◽  
Sine Wave ◽  
Lookup Table ◽  
Frequency Resolution ◽  
Digital Frequency ◽  
Quarter Wave ◽  
Direct Digital Frequency Synthesizer ◽  
Gated Clock

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

scholarly journals IMPLEMENTATION OF 32-BIT HIGH-VALENCY LING ADDER IN MODIFIED FIR FILTER USING APC-OMS APPROACH

2014 ◽  
pp. 122-126
Author(s):  
K. V. SURESH KUMAR ◽  
S. SHABBIR ALI ◽  
E. CHITRA
Keyword(s):  
Logic Gates ◽  
Lookup Table ◽  
Binary Number ◽  
Single Node ◽  
Input Size ◽  
Delay Measurement ◽  
Parallel Prefix ◽  
Area X ◽  
Prefix Adders ◽  
Logic Unit

Ling Adder is an advanced architecture of Parallel prefix adders. Parallel Prefix adders are used for efficient VLSI implementation of binary number additions. Ling architecture offers a faster carry computation stage compared to the conventional parallel prefix adders. Ling adders help to reduce the complexity as well as the delay of the adder further. In many computers and other kinds of processors, adders are used not only in the Arithmetic Logic Unit (ALUs), but also in other parts of the processor. Thus the delay in adders has to be decreased as maximum as possible to make the system faster. In particular, valency or the number of inputs to a single node is explored as a design parameter. High-valency Ling adders have superior area x delay characteristics over previously reported Ling-based or non-Ling based adders for the same input size. In DSP, even the multipliers require a large number of logic gates that consumes more area, power and delay. Hence, the lookup table can be used for performing computation which requires less area. Therefore, APC and OMS are the two techniques implemented in Lookup table so as to reduce the size to one-fourth of its conventional multiplier. This proposed combination of both Lookup table Multiplier and Ling adder has a better area and delay measurement.

Kinematic Analysis of a 5-DOF Positioner for Precision Additive Manufacturing

2020 ◽  
Author(s):  
Mohammad Hossein Saadatzi ◽  
Dan O. Popa
Keyword(s):  
Additive Manufacturing ◽  
High Precision ◽  
Error Propagation ◽  
Great Level ◽  
End Effector ◽  
Kinematic Chains ◽  
Design And Optimization ◽  
Positioning Errors ◽  
Error Propagation Analysis ◽  
Kinematic Sensitivity

Abstract Additive manufacturing, as a viable industrial-production technology, requires multi-DOF positioning with high precision and repeatability for either the printer head, or the part being printed. In this paper we present a novel methodology to analyze the error propagation informing the design of a high-precision robotic 5-DOF positioner for applications in additive manufacturing. We designed our positioner through serial attachment of linear and rotational stages by comparing the precision of three different kinematic arrangements of stages. Within order to minimize positioning errors in Cartesian space, the kinematic sensitivity of the mechanisms end-effector relative to the maximum expected error of each joint was computed, and the kinematic configuration with smallest 6D positioning error at the end-effector was selected. The methodology employed in this paper for the error propagation analysis of serial kinematic chains has a great level of generality and can facilitate the design and optimization of a wide-class of multi-DOF positioners.

An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation

2015 ◽  
Vol 24 (10) ◽  
pp. 1550151
Author(s):  
Wei Guo ◽  
KwangHyok Ri ◽  
Luping Cui ◽  
Jizeng Wei
Keyword(s):  
Logic Gates ◽  
Lookup Table ◽  
Floating Point ◽  
Cmos Process ◽  
Double Precision ◽  
Square Root ◽  
Area Efficiency ◽  
Area Reduction ◽  
Efficiency Performance ◽  
Performance Area

In this paper, we propose a unified architecture for computation of double-precision floating-point division, reciprocal, square root, inverse square root and multiplication with a significant area reduction. First, a double-precision multiplication-based divider, the common datapath shared with these arithmetic computations, is optimized by a modified Goldschmidt algorithm to achieve better area efficiency. In this algorithm, a linear-degree minimax approximation instead of second-degree is used to obtain a 15-bit precision estimate of the reciprocal so that we can get a rather small lookup table (LUT) as well as reduced amount of computation when accumulating the partial products. Two Goldschmidt iterations specially designed for hardware reuse are performed to gain the final accurate result of division. By virtue of the pipelined processing, the time cost for the two iterations is minimized. Second, a reconfigurable datapath with a little extra area cost is introduced to dynamically support multiple double-precision computations by executing the optimized divider iteratively. The design is finally implemented and synthesized in SMIC 0.13-μm CMOS process. The experimental results show that the proposed design can achieve a speed of 400 MHz with area of 61.6 K logic gates and 9-Kb LUT. Compared with other works, the area efficiency (performance/area ratio) of the proposed unified architecture is increased by about 20% in average, which is a better performance-area trade-off for embedded microprocessors.

scholarly journals Resolvable mating-environmental designs for partial triallel cross experiments

2021 ◽  
Vol 81 (01) ◽  
pp. 111-118
Author(s):  
Mohd Harun ◽  
Cini Varghese ◽  
Seema Jaggi ◽  
Eldho Varghes
Keyword(s):  
High Precision ◽  
Combining Ability ◽  
Constant Error ◽  
Orthogonal Design ◽  
Error Variance ◽  
General Combining Ability ◽  
Efficiency Factor ◽  
Specific Combining Ability ◽  
Low Degree ◽  
Different Types

Triallel crosses can be readily exploited as breeding tool for developing commercial hybrids with traits of genetical and commercial importance by acquiring information on specific combining ability effects along with general combining ability effects if the experimentation size is reduced to an economical extent. In this paper, methods of constructing designs involving partial triallel crosses in smaller blocks using different types of lattice designs have been introduced. The designs have low degree of fractionation, which suggests their utility when there is a resource crunch. Canonical efficiency factor of these designs relative to an orthogonal design with same number of lines, assuming constant error variance for both situations, is high indicating that adoption of these designs for the trials could bring about improvement as the recommendations from the experiment will be associated with a high precision.

scholarly journals SELF-TIMED LOOK UP TABLE FOR ULAs AND FPGAs

2021 ◽  
Vol 1 (1) ◽  
pp. 36-45
Author(s):  
S. F. Tyurin ◽  
A. Yu. Skornyakova ◽  
Y. A. Stepchenkov ◽  
Y. G. Diachenko
Keyword(s):  
Logic Gates ◽  
Transition Process ◽  
The Self ◽  
Lookup Table ◽  
Analysis And Design ◽  
Digital Devices ◽  
Digital Era ◽  
Analysis And Synthesis ◽  
Timed Circuits ◽  
Logic Array

Context. Self-Timed Circuits, proposed by D. Muller on the rise of the digital era, continues to excite researchers’ minds. These circuits started with the task of improving performance by taking into account real delays. Then Self-Timed Circuits have moved into the field of green computing. At last, they are currently positioned mainly in the field of fault tolerance. There is much redundancy in Self-Timed Circuits. It is believed that Self-Timed Circuits approaches will be in demand in the nano-circuitry when a synchronous approach becomes impossible. Strictly Self-Timed Circuits check transition process completion for each gate’s output. For this, they use so-called D. Muller elements (C-elements, hysteresis flip-flops, G-flip-flops). Usually, Self-Timed Circuits are designed on Uncommitted Logic Array. Now an extensive base of Uncommitted Logic Array Self-Timed gates exists. It is believed that SelfTimed Circuits are not compatible with FPGA technology. However, attempts to create self-timed FPGAs do not stop. The article proposes a Self-Timed Lookup Table for the Self-Timed Uncommitted Logic Array and the Self-Timed FPGA, carried out either by constants or utilizing additional memory cells. Authors proposed 1,2 – Self-Timed Lookup Table and described simulation results. Objective. The work’s goal is the analysis and design of the Strictly Self-Timed universal logic element based on Uncommitted Logic Array cells and pass-transistors circuits. Methods. Analysis and synthesis of the Strictly Self-Timed circuits with Boolean algebra. Simulation of the proposed element in the CAD “ARC”, TRANAL program, system NI Multisim by National Instruments Electronics Workbench Group, and layout design by Microwind. The reliability theory and reliability calculations in PTC Mathcad. Results. Authors designed, analyzed, and proved the Self-Timed Lookup Table’s workability for the Uncommitted Logic Arrays and FPGAs. Layouts of the novel logic gates are ready for manufacturing. Conclusions. The conducted studies allow us to use proposed circuits in perspective digital devices.

Laser interferometry measurements based calibration and error propagation identification for pose estimation in mobile robots

Robotica ◽  
2013 ◽  
Vol 32 (1) ◽  
pp. 165-174 ◽  
Author(s):  
Paulo A. Jiménez ◽  
Bijan Shirinzadeh
Keyword(s):  
Mobile Robots ◽  
Pose Estimation ◽  
Error Propagation ◽  
Laser Interferometry ◽  
Error Variance ◽  
Calibration Method ◽  
Novel Method ◽  
Position And Orientation ◽  
Odometry Calibration ◽  
Two Parameter

SUMMARYA widely used method for pose estimation in mobile robots is odometry. Odometry allows the robot in real time to reconstruct its position and orientation from the wheels' encoder measurements. Given to its unbounded nature, odometry calculation accumulates errors with quadratic increase of error variance with traversed distance. This paper develops a novel method for odometry calibration and error propagation identification for mobile robots. The proposed method uses a laser-based interferometer to measure distance precisely. Two variants of the proposed calibration method are examined: the two-parameter model and the three-parameter model. Experimental results obtained using a Khepera 3 mobile robot showed that both methods significantly increase accuracy of the pose estimation, validating the effectiveness of the proposed calibration method.

scholarly journals Feasibility study of high-precision trigonometric elevation replacing second-order level in tunnel penetration control survey

2020 ◽  
Vol 165 ◽  
pp. 04022
Author(s):  
Zhang Hongfeng
Keyword(s):  
Measurement Error ◽  
High Precision ◽  
Feasibility Study ◽  
Error Propagation ◽  
Measurement Accuracy ◽  
Second Order ◽  
Total Station ◽  
Level Measurement ◽  
Control Survey ◽  
Elevation Measurement

Based on the principle of trigonometric elevation measurement and the law of error propagation, the trigonometric elevation formula is derived in this paper. The factors that cause the trigonometric measurement error are analyzed accurately. It is considered that the use of a high-precision total station for the trigonometric elevation measurement under opposite conditions can reach the second-order level measurement accuracy.

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