Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs

2022 ◽  
Vol 15 (3) ◽  
pp. 1-25
Author(s):  
S. Rasoul Faraji ◽  
Pierre Abillama ◽  
Kia Bazargan
Keyword(s):  
Discrete Cosine Transform ◽  
Video Processing ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Logic Gates ◽  
Cosine Transform ◽  
Real Time Processing ◽  
Coefficient Multiplier ◽  
Encoding Method

Multipliers are used in virtually all Digital Signal Processing (DSP) applications such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is needed, as in 4K video processing, or where hardware resources are limited, as in mobile and IoT devices. We propose a novel, low-cost, low energy, and high-speed approximate constant coefficient multiplier (CCM) using a hybrid binary-unary encoding method. The proposed method implements a CCM using simple routing networks with no logic gates in the unary domain, which results in more efficient multipliers compared to Xilinx LogiCORE IP CCMs and table-based KCM CCMs (Flopoco) on average. We evaluate the proposed multipliers on 2-D discrete cosine transform algorithm as a common DSP module. Post-routing FPGA results show that the proposed multipliers can improve the {area, area × delay, power consumption, and energy-delay product} of a 2-D discrete cosine transform on average by {30%, 33%, 30%, 31%}. Moreover, the throughput of the proposed 2-D discrete cosine transform is on average 5% more than that of the binary architecture implemented using table-based KCM CCMs. We will show that our method has fewer routability issues compared to binary implementations when implementing a DCT core.

scholarly journals A Review of Self-Coherent Optical Transceivers: Fundamental Issues, Recent Advances, and Research Directions

2021 ◽  
Vol 11 (16) ◽  
pp. 7554
Author(s):  
Isiaka Alimi ◽  
Romil Patel ◽  
Nuno Silva ◽  
Chuanbowen Sun ◽  
Honglin Ji ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Dynamic Environment ◽  
Digital Signal ◽  
Research Directions ◽  
Recent Advances ◽  
Heterogeneous Nature ◽  
Signal Processing Algorithms ◽  
Processing Algorithms

This paper reviews recent progress on different high-speed optical short- and medium-reach transmission systems. Furthermore, a comprehensive tutorial on high-performance, low-cost, and advanced optical transceiver (TRx) paradigms is presented. In this context, recent advances in high-performance digital signal processing algorithms and innovative optoelectronic components are extensively discussed. Moreover, based on the growing increase in the dynamic environment and the heterogeneous nature of different applications and services to be supported by the systems, we discuss the reconfigurable and sliceable TRxs that can be employed. The associated technical challenges of various system algorithms are reviewed, and we proffer viable solutions to address them.

scholarly journals Decimation of Delta-Sigma-Modulated Signals Using a Low-Cost Microcontroller

2021 ◽  
Author(s):  
Markeljan Fishta ◽  
Franco Fiori
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Experimental Tests ◽  
General Purpose ◽  
Data Conversion ◽  
Clock Frequency ◽  
Main Challenge ◽  
Modulated Signals

Abstract$$\varDelta \varSigma $$ Δ Σ analog-to-digital converters (ADCs) are largely used in sensor acquisition applications. In the last few years, standalone $$\varDelta \varSigma $$ Δ Σ modulators have become increasingly available as off-the-shelf parts. To build a complete ADC, a standalone modulator has to be paired with some advanced elaboration unit, such as a field programmable gate array (FPGA) or a digital signal processor (DSP), which is needed for the implementation of the decimation filter. This work investigates the use of low-cost, general-purpose microcontrollers for the decimation of $$\varDelta \varSigma $$ Δ Σ -modulated signals. The main challenge is given by the clock frequency of the modulator, which can be in the range of a few $$\hbox {MHz}$$ MHz . The proposed technique deals with this limitation by employing two serial peripheral interface (SPI) modules in a time-interleaved configuration. This approach allows for continuous acquisition and elaboration of relatively high-speed, digital signals. The technique has been applied to a case study, and a data conversion system has been practically realized. The performance of the proposed filter is compared to that of a digital filter, present on board a commercial microcontroller, and the results of experimental tests are provided.

PC104 Interface Recommended for High Speed Data Acquisition Systems

2013 ◽  
Vol 325-326 ◽  
pp. 926-929 ◽  
Author(s):  
Dorina Purcaru ◽  
Cornelia Gordan ◽  
Romulus Reiz ◽  
Anca Purcaru
Keyword(s):  
Data Acquisition ◽  
High Speed ◽  
Low Cost ◽  
Sampling Rate ◽  
Digital Signal ◽  
Signal Acquisition ◽  
Synchronized Sampling ◽  
Data Acquisition Systems ◽  
High Speed Data Acquisition ◽  
High Speed Data

The interface presented in this paper is recommended for high speed data acquisition systems; it performs a synchronized sampling of all common-mode or differential analog inputs with a high sampling rate. This is a low cost interface, entirely controlled by the PC104 CPU. Programmable electronic modules that contain such PC104 interfaces can be found running in the energetic system from Romania; these dedicated equipments perform the analog and digital signal acquisition for monitoring and recording different specific transient events. Some experimental results obtained using the disturbance monitoring device PC-08/104 are also presented in this paper.

Design and Implementation of Audio Process System Based on DSP

2014 ◽  
Vol 945-949 ◽  
pp. 1752-1755
Author(s):  
Chui Xin Chen ◽  
Yang Hong Mao
Keyword(s):  
Real Time ◽  
Digital Signal Processor ◽  
High Speed ◽  
Audio Signal ◽  
Reference Value ◽  
Digital Signal ◽  
Real Time Processing ◽  
Audio Processing ◽  
Time Processing ◽  
Process System

The real-time processing for the input analog audio signal, audio processing program is proposed based on DSP. The system use FFT algorithm as the core, first, the input analog audio signal is sampled and A/D conversion using TLV320AIC23, and then use high speed digital signal processor to make real-time processing for the signal. Theoretical and experimental results show that the system can meet the design requirements, it has the advantage of high real-time and simple structure. The system has a good application and reference value for the development and design of data collecting and remote monitoring.

scholarly journals FPGA Implementation of Fault Tolerant & High Speed Reversible Systolic Multiplier

2020 ◽  
pp. 537-542
Keyword(s):  
High Speed ◽  
Fault Tolerant ◽  
Digital Signal ◽  
Logic Gates ◽  
Digital World ◽  
Essential Components ◽  
Static Power ◽  
Toffoli Gates ◽  
Reversible Logic Gates ◽  
Systolic Multiplier

Multiplier is one of the essential components in the digital world such as in digital signal processing, quantum computing, microprocessor and widely used in arithmetic unit. The Reversible rationale is a used to decrease heat scattering and data misfortune. Contrasted with all essential math activities, multiplication requests all the more preparing time and look for complex equipment. This paper presents a plan of low power Systolic Array Multiplier utilizing Reversible logic gates which performs information handling in parallel. In this paper, we present a high speed 4x4 Systolic Multiplier design by using peres gate and toffoli gates and source code written in verilog and also implemented on FPGA Spartan 3s50pq208-4. The synthesis and simulation is done on Xilinx ISE 14.7. The delay is 17.642ns and static power dissipation is 24mW.

scholarly journals An Accumulator using Electron Tunneling Through Tunnel Junction

2021 ◽  
pp. 163-183
Author(s):  
Dr. Anup Kumar Biswas
Keyword(s):  
High Speed ◽  
Electron Tunneling ◽  
Low Cost ◽  
Logic Gate ◽  
Logic Gates ◽  
Threshold Logic ◽  
High Concentration ◽  
Flip Flop ◽  
Linear Threshold ◽  
Parameter Values

Instead of an existing logical Technology, by using an emerging technology we will be able to make an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is based on the linear threshold logic condition and electron-tunneling event. At the time of implementing a circuit, a multi-inputs but one-output based logic-node will be brought in our consideration. In this work, we have designed a 1-bit accumulator and then implemented it. To develop an accumulator, some small components like 2-input AND, 3-input AND, 3-input OR, 8-input OR, 9-input OR gate and above all a JK Flip-flop (for 1-bit) are to be collected and connected them in logical order to obtain the proper circuit. After verifying all their characteristics with the results obtained from the simulator, we have built a 1-bit accumulator. All the small components are provided in due places. They are analyzed, detected their threshold logic equations, shown their threshold logic gates (TLGs), tabulated their truth tables, drawn their input-output waveforms, given their respective circuits with exact parameter values. In the accumulator, there are nine control variables S1 through S9 in view of performing the operations (i) Addition, (ii) clear, (iii) complement, (iv) AND, (v) OR, (vi) XOR, (vii) Right-shift, (viii) Left-shift and (ix) increment with positive triggering clock pulses. Whether our present work’s circuits are faster or slower with respect to the similar circuits of CMOS based- and Single electron transistor (SET) based circuits are compared and observed that our TLG based circuits are faster than the CMOS and SET based circuits. The power consumed for tunneling event for a circuit is measured and sensed that it would remain in the range of 10meV to 250meV which is low. All the circuits we have presented in this work are of ‘generic multiple input threshold logic gate’ which is elaborately discussed.

UTILIZATION OF HIGH-SPEED DSP ALGORITHMS OF CYCLIC REDUNDANCY CHECKING (CRC-15) ENCODER AND DECODER FOR CONTROLLER AREA NETWORK

2016 ◽  
Vol 78 (5-9) ◽  
Author(s):  
Ronnie O. Serfa Juan ◽  
Hi Seok Kim
Keyword(s):  
Error Detection ◽  
High Speed ◽  
Clock Synchronization ◽  
Transmission Rate ◽  
Critical Path ◽  
Low Cost ◽  
Digital Signal ◽  
Transmission Error ◽  
Controller Area Network ◽  
Area Network

Advanced driver assistance system (ADAS) performs an increasing improvement in active road safety and driving convenience. Controller Area Network (CAN) is now getting popular because of its expanding applications and widely utilizations in low-cost embedded systems from automation to medical industry. While implementing an effective and efficient mechanism for clock synchronization, serial operation causes the reduction of CAN transmission rate can have an adverse impact on the real-time applications of systems employing this protocol. Also, maintaining the reliability of this technology especially in safety services, a reliable system needs certain requirements like glitches management and troubleshooting in order to avoid certain occurrences of transmission error.  In this paper we present a simulated Cyclic Redundancy Checking (CRC) encoder and decoder that perform high speed error detection for CAN using CRC-15. Digital Signal Processing (DSP) algorithms were used, namely pipelining, unfolding and retiming to attain the feasible iteration bound and critical path that is appropriate for CAN system. The source code for Encoder and Decoder has been formulated in Verilog Hardware Description Language (HDL) from actual simulation to implementation of this CRC-15 for CAN system.

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