scholarly journals AES High-Level SystemC Modeling using Aspect Oriented Programming Approach

2021 ◽  
Vol 11 (1) ◽  
pp. 6719-6723
Author(s):  
H. Mestiri ◽  
I. Barraj ◽  
M. Machhout
Keyword(s):  
Electronic System ◽  
System Level ◽  
Functional Verification ◽  
Programming Approach ◽  
Aspect Oriented Programming ◽  
Simulation Speed ◽  
Executable File ◽  
High Level ◽  
The Impact ◽  
Simulation Time

The increasing complexity of the cryptographic modeling and security simulation of the Advanced Encryption Standard (AES) necessitate fast modeling and simulation security environment. The SystemC language is used in Electronic System Level (ESL) that allows cryptographic models to achieve high security and modeling simulation speed. Yet, the use of SystemC in the security simulation requires modifications of the original code which increases the modeling complexity. The Aspect-Oriented Programming (AOP) can be used in the cryptographic modeling and security simulations without any code modification. In this paper, a new AES SystemC model using the AOP technique is presented. A functional verification environment is proposed to test the functionality of the AES SystemC AOP model, the impact of AOP on simulation time, and the size of the executable files. The design of the AES model is developed with the weaving of all modules by AspectC++ which is an AOP language. The Simulation results show the efficiency of the proposed AES model and the uses of the AOP technique do not have a significant impact on simulation time or on the size of the executable file.

An AOP-Based Fault Injection Environment for Cryptographic SystemC Designs

2014 ◽  
Vol 24 (01) ◽  
pp. 1550008 ◽  
Author(s):  
Hassen Mestiri ◽  
Younes Lahbib ◽  
Mohsen Machhout ◽  
Rached Tourki
Keyword(s):  
Fault Injection ◽  
Electronic System ◽  
System Level ◽  
Standard Case ◽  
Fault Attacks ◽  
Injection Attacks ◽  
Electronic System Level ◽  
Fault Injection Attacks ◽  
The Impact ◽  
Simulation Time

The increasing complexity of cryptographic devices requires fast simulation environment in order to test their security against fault attacks. SystemC is one promising candidate in Electronic System Level that allows models to reach higher simulation speed. However in order to enable both fault injection and detection inside a SystemC cryptographic models, its code modification is mandatory. Aspect-Oriented Programming (AOP), which is a new programming paradigm, can be used to test the robustness of the cryptographic models without any code modifications. This may replace real cryptanalysis schemes. In this paper, we present a new methodology to simulate the security fault attacks of cryptographic systems at the Electronic System Level. A fault injection/detection environment is proposed to test the resistance of cryptographic SystemC models against fault injection attacks. The fault injection technique into cryptographic SystemC models is performed using weaving faults by AspectC++ as an AOP programming language. We validate our methodology with two scenarios applied to a SystemC Advanced Encryption Standard case study: the first is related to the impact of the AOP on fault detection capabilities, while the second refers to the impact of the AOP on simulation time and size of the executable files. Simulation results show that this methodology can evaluate perfectly the robustness of a cryptographic design against fault injection attacks. They show that the impact of AOP on simulation time is not significant.

High-Level Implementation of a Chaotic and AES Based Crypto-System

2017 ◽  
Vol 26 (07) ◽  
pp. 1750122 ◽  
Author(s):  
Fatma Sbiaa ◽  
Sonia Kotel ◽  
Medien Zeghid ◽  
Rached Tourki ◽  
Mohsen Machhout ◽  
...  
Keyword(s):  
Electronic System ◽  
Performance Criteria ◽  
System Level ◽  
Security Level ◽  
Sensitive Data ◽  
Aes Algorithm ◽  
Simulation Speed ◽  
Key Space ◽  
High Security Level ◽  
High Level

Given the increasing complexity of cryptographic devices, testing their security level against existing attacks requires a fast simulation environment. SystemC is a standard language that is widely used for the modeling and the verification of complex systems. It is a promising candidate in Electronic System Level (ESL) which allows models to reach higher simulation speed. Accordingly, the Advanced Encryption Standard (AES) is one of the most known block ciphers. It is widely used in various applications in order to secure the sensitive data. It is considered to be secure. Still, some issues lie in the used key and the S-Box. This paper presents a SystemC implementation of a chaos-based crypto-processor for the AES algorithm. The design of the proposed architecture is studied using the SystemC tools. The proposed correction approach exploits the chaos theory properties to cope with the defaulting parameters of the AES algorithm. Detailed experimental results are given in order to evaluate the security level and the performance criteria. In fact, the proposed crypto-system presents numerous interesting features, including a high security level, a pixel distributing uniformity, a sufficiently large key-space with improved key sensitivity, and an acceptable speed.

Fast Transaction-Level Model for Direct Memory Access Controller

2019 ◽  
Vol 28 (04) ◽  
pp. 1950059
Author(s):  
Mona Safar ◽  
Magdy A. El-Moursy ◽  
Ahmed Tarek ◽  
Ahmed Emad ◽  
Ahmed Hesham ◽  
...  
Keyword(s):  
Open Source ◽  
Direct Memory Access ◽  
System Level ◽  
The Past ◽  
Simulation Speed ◽  
Proposed Model ◽  
Level Model ◽  
Data Bus ◽  
Transaction Level ◽  
Simulation Time

Transaction-Level Modeling (TLM) has been widely used in system-level design in the past few years. Simulation speed of Virtual Platforms (VPs) depends mainly on the transactions which are initiated by the Programmer’s View (PV) models of the VP devices. PV models are required to run at highest simulation speed. Data bus width as a hardware (HW) parameter should not reduce simulation speed of the modeled transactions. Furthermore, HW-related parameters should only be accounted for when considering timing of the models. A fast SystemC-TLM model is developed for the widely used ARM PrimeCell PL080 DMAC IP. The performance of the proposed model is validated against a developed RTL model for the same device. The effect of the transactions granularity on simulation speed is determined. Different programmed transfers are simulated and compared with open-source Quick Emulator (QEMU)-based models. The developed model is compared with the developed RTL, the open-source QEMU model, and the existing ARM Fast Model (AFM). It is shown that simulation time of the developed model is reduced by two orders of magnitude as compared to the other existing models.

A high-level requirements engineering methodology for electronic system-level design

2007 ◽  
Vol 33 (4) ◽  
pp. 249-268 ◽  
Author(s):  
N. Gorse ◽  
P. Bélanger ◽  
A. Chureau ◽  
E.M. Aboulhamid ◽  
Y. Savaria
Keyword(s):  
Requirements Engineering ◽  
Electronic System ◽  
System Level ◽  
System Level Design ◽  
Electronic System Level ◽  
Level Design ◽  
High Level

scholarly journals An Approach for Power Estimation at Electronic System Level using Distributed Simulation

2016 ◽  
Vol 11 (3) ◽  
pp. 159-170
Author(s):  
Helder F. A. Oliveira ◽  
Alisson V. Brito ◽  
Joseana M. F. R. Araujo ◽  
Elmar U. K. Melcher
Keyword(s):  
Distributed Simulation ◽  
Power Estimation ◽  
Electronic System ◽  
System Level ◽  
Multiprocessor System ◽  
High Level Architecture ◽  
Electronic System Level ◽  
On Chip ◽  
High Level ◽  
Abstraction Levels

The present research aims to develop an approach using HLA (High Level Architecture), enabling the cre-ation of a distributed and heterogeneous environment, composed by different tools and models to obtain a better trade-off between accuracy and run time in power estimation. These models can be described in different languages and/or abstraction levels, as well as use different power estimation approaches. The use of HLA enables the synchronized and distributed simulation of the elements that compose the simulation environment. The approach must allow the collecting and grouping of power estimation data in a centralized manner. As a case study, an MPSoC (MultiProcessor System-on-Chip) ESL/TLM model, described in C++/SystemC, and an ESL model, created on Ptolemy framework, have been used. The experimental results show the flexibility of the approach, which promotes an integrated view of power estimation data.

scholarly journals Automatic synthesis of 2D‐n‐scrolls chaotic systems by behavioral modeling

2009 ◽  
Vol 7 (01) ◽  
Author(s):  
J. M. Muñoz-Pacheco ◽  
E. Tlelo-Cuautle
Keyword(s):  
Chaotic Systems ◽  
Piecewise Linear ◽  
Electronic System ◽  
System Level ◽  
Operational Amplifiers ◽  
Piecewise Linear Approximation ◽  
Chaotic Oscillator ◽  
State Variables ◽  
Breaking Points ◽  
High Level

This paper introduces the guidelines to synthesize 2D chaotic systems by means of high‐level descriptions. The aim of this investigation is to synthesize 2D‐n‐scrolls chaotic systems based on saturated functions with multisegments. The new methodology of circuit synthesis is performed by three hierarchical levels. First, the 2D chaotic oscillator is numerically simulated at the electronic system level by applying state variables and piecewise‐linear approximation. Second, the excursion levels of the chaotic signals are scaled to control the breaking points and slopes of the saturated functions within practical values. Additionally, the frequency scaling of 2D‐n‐scrolls chaotic attractors is performed. Finally, current and voltage saturated functions are synthesized using Verilog‐A models for the operational amplifiers and in this manner a 2D chaotic system is synthesized using operational amplifiers to generate 2D‐n‐scrolls attractors. Numerical results are confirmed by H‐SPICE simulations to show the usefulness of the proposed synthesis approach.

scholarly journals Functioning of a child with bilateral cerebral palsy submitted to multilevel surgery: case report

2021 ◽  
Vol 11 (4) ◽  
Author(s):  
Renata Martins Rosa ◽  
Elisa de Jesus Valenzuela ◽  
Erica Cesario Defilipo ◽  
Paula Silva de Carvalho Chagas
Keyword(s):  
Cerebral Palsy ◽  
Motor Function ◽  
Electronic System ◽  
Lower Limbs ◽  
System Level ◽  
Gross Motor ◽  
Gross Motor Function ◽  
Multilevel Surgery ◽  
Informed Consent Form ◽  
The Impact

INTRODUCTION: Interventions in different joints may be necessary to correct crouch gait and others musculoskeletal changes that occur as time passes for Cerebral Palsy (CP) children. Multilevel surgery reduces the number of hospitalizations, contributes to the prevention of secondary disabilities, and improves ambulation ability of children with diplegia. OBJECTIVE: Document the changes in mobility outcomes of a bilateral CP child, type diplegia, child after lower limbs multilevel surgery in the Brazilian context MATERIAL AND METHODS: The participant was an eight-year-old girl, Gross Motor Function Classification System level III. The mother signed the informed consent form. The Gross Motor Function Measure–66 (GMFM-66) was performed one day before surgery and one, three, six and twelve months after surgery. To complete the child’s evolution records, additional information was obtained through the electronic system of the hospital. RESULTS: The GMFM-66 total score was: 49.6 pre-operative (CI95%: 47.3-51.9); 42.8 after one month (CI95%: 40.7-45.0); 49.9 after three months (CI95%: 47.6-52.1); 52.6 after six months (CI95%: 50.2-55.0) and 56.9 after one year (CI95%: 54.6-59.2), increasing after 6 months of surgery (*p<0.05). The participant presented satisfactory adherence to physiotherapy. CONCLUSION: This study describes the case of a Brazilian child with CP, using the public health system. The impact of multilevel surgery was predominant in mobility, with worsening of capacity soon after surgery and progressive improvement over the months. Factors that may have contributed to our results were adherence, frequency, contextual factors.

scholarly journals Formal ESL Synthesis for Control-Intensive Applications

2012 ◽  
Vol 2012 ◽  
pp. 1-30 ◽  
Author(s):  
Michael F. Dossis
Keyword(s):  
Electronic System ◽  
System Level ◽  
Specific Design ◽  
Program Code ◽  
Electronic System Level ◽  
Executable Specifications ◽  
Real World Applications ◽  
High Level ◽  
Embedded Applications ◽  
Application Specific

Due to the massive complexity of contemporary embedded applications and integrated systems, long effort has been invested in high-level synthesis (HLS) and electronic system level (ESL) methodologies to automatically produce correct implementations from high-level, abstract, and executable specifications written in program code. If the HLS transformations that are applied on the source code are formal, then the generated implementation is correct-by-construction. The focus in this work is on application-specific design, which can deliver optimal, and customized implementations, as opposed to platform or IP-based design, which is bound by the limits and constraints of the preexisting architecture. This work surveys and reviews past and current research in the area of ESL and HLS. Then, a prototype HLS compiler tool that has been developed by the author is presented, which utilizes compiler-generators and logic programming to turn the synthesis into a formal process. The scheduler PARCS and the formal compilation of the system are tested with a number of benchmarks and real-world applications. This demonstrates the usability and applicability of the presented method.

scholarly journals Are HLS Tools Healthy? The C-Cubed Project

2015 ◽  
Vol 5 (2) ◽  
pp. 790-794
Author(s):  
M. Dossis ◽  
G. Dimitriou
Keyword(s):  
Integrated Circuits ◽  
Systems Engineering ◽  
Critical Role ◽  
Formal System ◽  
Electronic System ◽  
System Level ◽  
High Level Synthesis ◽  
Practical Reasons ◽  
Engineering Practice ◽  
High Level

The increasing complexity of Application Specific Integrated Circuits (ASICs) and Systems-on-Chip (SoCs) that incorporate custom and standard embedded core IP blocks dictates the need for a new generation of automated and formal system EDA tools and methodologies. High-Level Synthesis (HLS) plays a critical role in the required Electronic System Level (ESL) methodologies. However, most of the available academic and commercial High-Level Synthesis (HLS) tools still do not play an established role in the system and hardware engineering teams. This is true for a number of practical reasons, analyzed and discussed in this work. The present article is a practical perspective of the required fully automated and formal tools, which are needed to constitute integral parts in Electronic Design Automation (EDA) flows. In addition, this article is a useful guide to the system engineer who wants to familiarize with HLS tools and to select the appropriate tool for the everyday engineering practice. The advanced HLS toolset that is analyzed in this paper is developed by the first author, its C-frontend by the second author, and they are both based on formal methods and fully automated techniques, thus they guarantee the correctness of the synthesized hardware implementations. This paper completes with a number of experiments that were executed using the author’s methodology and they are used to evaluate the specific HLS tools. Consequently, a number of conclusions are drawn as well as suggestions for the future directions of HLS technology. In this way, what is practically needed by the hardware systems engineering community is outlined at the end of the paper.

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