scholarly journals Nanoscale Switching and Degradation of Resistive Random Access Memory Studied by In Situ Electron Microscopy

Author(s):  
Masashi Arita ◽  
Atsushi Tsurumaki-Fukuchi ◽  
Yasuo Takahashi
2015 ◽  
Vol 5 (1) ◽  
Author(s):  
Masashi Arita ◽  
Akihito Takahashi ◽  
Yuuki Ohno ◽  
Akitoshi Nakane ◽  
Atsushi Tsurumaki-Fukuchi ◽  
...  

2013 ◽  
Vol 21 (1) ◽  
pp. 170-176 ◽  
Author(s):  
Hyun Woo Nho ◽  
Jong Yun Kim ◽  
Jian Wang ◽  
Hyun-Joon Shin ◽  
Sung-Yool Choi ◽  
...  

Here, anin situprobe for scanning transmission X-ray microscopy (STXM) has been developed and applied to the study of the bipolar resistive switching (BRS) mechanism in an Al/graphene oxide (GO)/Al resistive random access memory (RRAM) device. To performin situSTXM studies at the CK- and OK-edges, both the RRAM junctions and theI0junction were fabricated on a single Si3N4membrane to obtain local XANES spectra at these absorption edges with more delicateI0normalization. Using this probe combined with the synchrotron-based STXM technique, it was possible to observe unique chemical changes involved in the BRS process of the Al/GO/Al RRAM device. Reversible oxidation and reduction of GO induced by the externally applied bias voltages were observed at the OK-edge XANES feature located at 538.2 eV, which strongly supported the oxygen ion drift model that was recently proposed fromex situtransmission electron microscope studies.


Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.


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