scholarly journals Industrial robot arm controller based on programmable System-on-Chip device

2021 ◽  
Vol 49 (4) ◽  
pp. 1025-1034
Author(s):  
Vo Cong
Keyword(s):  
Real Time ◽  
High Performance ◽  
Industrial Robot ◽  
Industrial Applications ◽  
System On Chip ◽  
Robot Arm ◽  
Single Chip ◽  
Arm Processor ◽  
Field Programmable ◽  
On Chip

Field-programmable gate arrays (FPGAs) and, recently, System on Chip (SoC) devices have been applied in a wide area of applications due to their flexibility for real-time implementations, increasing the processing capability on hardware as well as the speed of processing information in real-time. The most important applications based on FPGA/SoC devices are focused on signal/image processing, Internet of Things (IoT) technology, artificial intelligence (AI) algorithms, energy systems applications, automatic control and industrial applications. This paper develops a robot arm controller based on a programmable System-OnChip (SoC) device that combines the high-performance and flexibility of a CPU and the processing power of an FPGA. The CPU consists of a dual-core ARM processor that handles algorithm calculations, motion planning and manages communication and data manipulation. FPGA is mainly used to generate signals to control servo and read the feedback signals from encoders. Data from the ARM processor is transferred to the programmable logic side via the AXI protocol. This combination delivers superior parallel-processing and computing power, real-time performance and versatile connectivity. Additionally, having the complete controller on a single chip allows the hardware design to be simpler, more reliable, and less expensive.

Real-time audio signal processing using system-on-chip field programmable gate arrays

2019 ◽  
Vol 146 (4) ◽  
pp. 2879-2879
Author(s):  
Ross K. Snider ◽  
Trevor Vannoy ◽  
James Eaton ◽  
Matthew Blunt ◽  
E. Bailey Galacci ◽  
...  
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Audio Signal ◽  
Field Programmable Gate Arrays ◽  
System On Chip ◽  
Audio Signal Processing ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip

scholarly journals Remote TSN Frame Encapsulation by means of FPGA

2021 ◽  
Author(s):  
Jaime Jiménez ◽  
Igor Rodríguez ◽  
David Reguilón ◽  
Aitzol Zuloaga ◽  
Jesús Lázaro
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Industry 4.0 ◽  
Frame Analysis ◽  
System On Chip ◽  
The Other ◽  
Ideal Solution ◽  
Field Programmable ◽  
Real Time Transmission ◽  
On Chip

Abstract TSN (Time-Sensitive Networking) has replaced outdated Fieldbus and non-deterministic Ethernet in the Industry 4.0. Field buses are not capable of providing neither connection for industry 4.0 IoT (Internet of Things) nor compatibility between different manufacturers. On the other hand, Ethernet is not able to ensure real-time. On the contrary, TSN guarantees real-time transmission, IoT and compatibility between devices. However, adapting to frequently changing needs makes TSN protocol evolve continuously. For this reason, devices for TSN analysis, such as PCs or not advanced frame analysis equipment are not able to process TSN packets at the speed that standard advances, discarding them as wrong frames. The integration of a System on Chip (SoC) that contains an FPGA (Field Programmable Gate Array) and a microcontroller, with capacity for reconfiguration and monitoring of the frames in the protocol, would be an ideal solution to this problem. This paper describes how to encapsulate TSN frames in Ethernet packets using an FPGA. Such Ethernet frames can subsequently be decapsulated, i.e. in a PC, and thus enable analysing TSN traffic in nonspecialized devices.

scholarly journals Implementation of an ARM-based system using a Xilinx ZYNQ SoC

2019 ◽  
Vol 13 (2) ◽  
pp. 485
Author(s):  
Omar Salem Baans ◽  
Asral Bahari Jambek
Keyword(s):  
Embedded Systems ◽  
Field Programmable Gate Arrays ◽  
System On Chip ◽  
Software System ◽  
Gate Arrays ◽  
Arm Processor ◽  
Systems On Chip ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip

<span>ARM processors are widely used in embedded systems. They are often implemented as microcontrollers, field-programmable gate arrays (FPGAs) or systems-on-chip. In this paper, a variety of ARM processor platform implementations are reviewed, such as implementation into a microcontroller, a system-on-chip and a hybrid ARM-FPGA platform. Furthermore, the implementation of a specific ARM processor, the Cortex-A9 processor, into a system-on-chip (SoC) on an FPGA is discussed using Xilinx’s Vivado and SDK software system and execution on a Xilinx Zynq Board.</span>

scholarly journals System on Chip Based RTC in Power Electronics

2017 ◽  
Vol 6 (4) ◽  
pp. 358-363
Author(s):  
R. Dorothy ◽  
Sasilatha T.
Keyword(s):  
Real Time ◽  
Industrial Applications ◽  
Current Control ◽  
System On Chip ◽  
Internal Communication ◽  
Level Control ◽  
Real Time Control ◽  
Advantages And Disadvantages ◽  
Time Control ◽  
On Chip

Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested–but to the knowledge of the author’s seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.

Real-time implementation of an auditory nerve model using a system-on-chip field-programmable gate array

2020 ◽  
Vol 148 (4) ◽  
pp. 2468-2468
Author(s):  
Matthew Blunt ◽  
Hezekiah Austin ◽  
Trevor Vannoy ◽  
Tyler Davis ◽  
Ross Snider
Keyword(s):  
Real Time ◽  
Auditory Nerve ◽  
Field Programmable Gate Array ◽  
System On Chip ◽  
Field Programmable ◽  
Nerve Model ◽  
Gate Array ◽  
On Chip

scholarly journals High-Performance Time Server Core for FPGA System-on-Chip

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 528 ◽  
Author(s):  
Julian Viejo ◽  
Jorge Juan-Chico ◽  
Manuel J. Bellido ◽  
Paulino Ruiz-de-Clavijo ◽  
David Guerrero ◽  
...  
Keyword(s):  
High Performance ◽  
System On Chip ◽  
The Core ◽  
Performance Time ◽  
Network Time ◽  
Wide Range ◽  
Network Time Protocol ◽  
Field Programmable ◽  
And Performance ◽  
On Chip

This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core for field programmable gate arrays. The core uses a carefully designed modular architecture, which is fully implemented in hardware using digital circuits and systems. Most remarkable novelties introduced are a hardware-optimized timekeeping algorithm implementation, and a full-hardware protocol stack and automatic network configuration. As a result, the core is able to achieve similar accuracy and performance to typical high-performance network time protocol server equipment. The core uses a standard global positioning system receiver as time reference, has a small footprint and can easily fit in a low-range field-programmable chip, greatly scaling down from previous system-on-chip time synchronization systems. Accuracy and performance results show that the core can serve hundreds of thousands of network time clients with negligible accuracy degradation, in contrast to state-of-the-art high-performance time server equipment. Therefore, this core provides a valuable time server solution for a wide range of emerging embedded and distributed network applications such as the Internet of Things and the smart grid, at a fraction of the cost and footprint of current discrete and embedded solutions.

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