Diamond Field-Effect Transistors with 1.3 A/mm Drain Current Density by Al2O3Passivation Layer

2012 ◽  
Vol 51 (9R) ◽  
pp. 090112 ◽  
Author(s):  
Kazuyuki Hirama ◽  
Hisashi Sato ◽  
Yuichi Harada ◽  
Hideki Yamamoto ◽  
Makoto Kasu
Keyword(s):  
Current Density ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current

Normally-Off 4H-SiC Vertical JFET with Large Current Density

2008 ◽  
Vol 600-603 ◽  
pp. 1059-1062 ◽  
Author(s):  
Haruka Shimizu ◽  
Yasuo Onose ◽  
Tomoyuki Someya ◽  
Hidekatsu Onose ◽  
Natsuki Yokoyama
Keyword(s):  
Current Density ◽  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Large Current ◽  
Blocking Voltage ◽  
Large Current Density ◽  
Abrupt Junction ◽  
Junction Field Effect Transistors

We developed normally-off 4H-SiC vertical junction field effect transistors (JFETs) with large current density. The effect of forming an abrupt junction between the gate and the channel was simulated, and vertical JFETs were then fabricated with abrupt junctions. As a result, a large rated drain current density (500 A/cm2) and a low specific on-resistance (2.0 mWcm2) were achieved for small devices. The blocking voltage was 600 V. These results were due to a reduction of the threshold voltage by forming the abrupt junction between the gate and the channel.

Diamond Field-Effect Transistors with 1.3 A/mm Drain Current Density by Al$_{2}$O$_{3}$ Passivation Layer

2012 ◽  
Vol 51 ◽  
pp. 090112 ◽  
Author(s):  
Kazuyuki Hirama ◽  
Hisashi Sato ◽  
Yuichi Harada ◽  
Hideki Yamamoto ◽  
Makoto Kasu
Keyword(s):  
Current Density ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Passivation Layer

Preparation of integrated chemical sensors using commercial VLSI technology

1987 ◽  
Vol 65 (5) ◽  
pp. 1072-1078 ◽  
Author(s):  
Paul G. Glavina ◽  
D. Jed Harrison
Keyword(s):  
Chemical Sensors ◽  
Linear Response ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Microelectrode Arrays ◽  
Drain Current ◽  
Cyclic Voltammetric ◽  
Design Rules ◽  
Vlsi Technology ◽  
Commercial Technology

The fabrication of ion sensitive field effect transistors (ISFET) and microelectrode arrays for use as chemical sensors using a commercial CMOS fabrication process is described. The commercial technology is readily available through the Canadian Microelectronics Corporation; however, several of the recommended design rules must be ignored in preparing chemical sensors using this process. The ISFET devices show near theoretical response to K+ in aqueous solution (55 mV slope) when coated with a K+ sensitive membrane. An extended gate ion sensitive device is presented which offers advantages in encapsulation of ISFET sensors. The source-drain current of both devices show a linear response to log [Formula: see text] in contrast to ISFETs previously reported that have high internal lead resistances. Al and poly-Si microelectrode arrays are fabricated commercially and then Pt is electrodeposited on the microelectrodes. The resulting arrays show good cyclic voltammetric response to Fe(CN)64− and Ru(NH3)63+ and are relatively durable.

AlGaN/GaN Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors (MOSHFETs) with the Delta-Doped Barrier Layer

2002 ◽  
Vol 743 ◽  
Author(s):  
Z. Y. Fan ◽  
J. Li ◽  
J. Y. Lin ◽  
H. X. Jiang ◽  
Y. Liu ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Cutoff Frequency ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Heterostructure ◽  
Heterostructure Field Effect Transistors ◽  
Gate Control

ABSTRACTThe fabrication and characterization of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with the δ-doped barrier are reported. The incorporation of the SiO2 insulated-gate and the δ-doped barrier into HFET structures reduces the gate leakage and improves the 2D channel carrier mobility. The device has a high drain-current-driving and gate-control capabilities as well as a very high gate-drain breakdown voltage of 200 V, a cutoff frequency of 15 GHz and a maximum frequency of oscillation of 34 GHz for a gate length of 1 μm. These characteristics indicate a great potential of this structure for high-power-microwave applications.

Temporal Changes in Source–Drain Current for Organic Field-Effect Transistors Caused by Dipole on Insulator Surface

2008 ◽  
Vol 1 ◽  
pp. 061801 ◽  
Author(s):  
Kouji Suemori ◽  
Misuzu Taniguchi ◽  
Sei Uemura ◽  
Manabu Yoshida ◽  
Satoshi Hoshino ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Temporal Changes ◽  
Organic Field Effect Transistors ◽  
Insulator Surface

Influence of work function variation of metal gates on fluctuation of sub-threshold drain current for fin field-effect transistors with undoped channels

2014 ◽  
Vol 53 (4S) ◽  
pp. 04EC11 ◽  
Author(s):  
Takashi Matsukawa ◽  
Yongxun Liu ◽  
Kazuhiko Endo ◽  
Junichi Tsukada ◽  
Hiromi Yamauchi ◽  
...  
Keyword(s):  
Work Function ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Metal Gates

scholarly journals Line-Edge Roughness from Extreme Ultraviolet Lithography to Fin-Field-Effect-Transistor: Computational Study

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1493
Author(s):  
Sang-Kon Kim
Keyword(s):  
Field Effect ◽  
Extreme Ultraviolet ◽  
Field Effect Transistors ◽  
Computational Study ◽  
Drain Current ◽  
Extreme Ultraviolet Lithography ◽  
Line Edge Roughness ◽  
Stochastic Fluctuation ◽  
Ultraviolet Lithography ◽  
Edge Roughness

Although extreme ultraviolet lithography (EUVL) has potential to enable 5-nm half-pitch resolution in semiconductor manufacturing, it faces a number of persistent challenges. Line-edge roughness (LER) is one of critical issues that significantly affect critical dimension (CD) and device performance because LER does not scale along with feature size. For LER creation and impacts, better understanding of EUVL process mechanism and LER impacts on fin-field-effect-transistors (FinFETs) performance is important for the development of new resist materials and transistor structure. In this paper, for causes of LER, a modeling of EUVL processes with 5-nm pattern performance was introduced using Monte Carlo method by describing the stochastic fluctuation of exposure due to photon-shot noise and resist blur. LER impacts on FinFET performance were investigated using a compact device method. Electric potential and drain current with fin-width roughness (FWR) based on LER and line-width roughness (LWR) were fluctuated regularly and quantized as performance degradation of FinFETs.

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