Analytical Modeling of Read Margin Probability Distribution Function of Static Random Access Memory Cells in Presence of Process Variations and Negative Bias Temperature Instability Effect

Abstract. In current process technologies, NBTI (negative bias temperature instability) has the most severe aging effect on static random access memory (SRAM) cells. This degradation effect causes loss of stability. In this paper countermeasures against this hazard are presented and quantified via simulations in 90 nm process technologies by the established metrics SNMread, SNMhold, Iread and Write Level. With regard to simulation results and practicability best candidates are chosen and, dependent on individual preferences at memory cell design, the best countermeasure in each case is recommended.

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The analysis of static random access memory stability under the influence of statistical variability and bias temperature instability-induced ageing

Semiconductor Science and Technology ◽

10.1088/1361-6641/abcbd6 ◽

2020 ◽

Vol 36 (2) ◽

pp. 025008

Author(s):

Jie Ding ◽

Asen Asenov

Keyword(s):

Random Access ◽

Random Access Memory ◽

Static Random Access Memory ◽

Access Memory ◽

Temperature Instability ◽

Bias Temperature Instability ◽

Statistical Variability

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Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1998p0373 ◽

1998 ◽

Author(s):

Phil Schani ◽

S. Subramanian ◽

Vince Soorholtz ◽

Pat Liston ◽

Jamey Moss ◽

...

Keyword(s):

Electron Microscopy ◽

Random Access ◽

Random Access Memory ◽

Static Random Access Memory ◽

Temperature Sensitive ◽

Wafer Level ◽

Top Down ◽

Access Memory ◽

Transmission Electron ◽

Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

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Challenges and Benefits of Product-Like SRAM in Technology Development

ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2011p0362 ◽

2011 ◽

Author(s):

Felix Beaudoin ◽

Stephen Lucarini ◽

Fred Towler ◽

Stephen Wu ◽

Zhigang Song ◽

...

Keyword(s):

Technology Development ◽

Random Access ◽

Random Access Memory ◽

Static Random Access Memory ◽

Development Phase ◽

High Complexity ◽

Access Memory ◽

Integration Schemes ◽

Front End

Abstract For SRAMs with high logic complexity, hard defects, design debug, and soft defects have to be tackled all at once early on in the technology development while innovative integration schemes in front-end of the line are being validated. This paper presents a case study of a high-complexity static random access memory (SRAM) used during a 32nm technology development phase. The case study addresses several novel and unrelated fail mechanisms on a product-like SRAM. Corrective actions were put in place for several process levels in the back-end of the line, the middle of the line, and the front-end of the line. These process changes were successfully verified by demonstrating a significant reduction of the Vmax and Vmin nest array block fallout, thus allowing the broader development team to continue improving random defectivity.

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