Two-dimensional semi-analytical model of subthreshold surface potential and drain current for double-doping polysilicon gate MOSFET

2015 ◽  
Vol 54 (5) ◽  
pp. 054202
Author(s):  
Hui-Fang Xu ◽  
Yue-Hua Dai ◽  
Jian-Bin Xu ◽  
Ning Li ◽  
Jin Yang ◽  
...  
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Drain Current ◽  
Two Dimensional ◽  
Double Doping ◽  
Polysilicon Gate

scholarly journals Study of Matching Properties of Graded-Channel SOI MOSFETs

2008 ◽  
Vol 3 (2) ◽  
pp. 69-75
Author(s):  
Michelly De Souza ◽  
Denis Flandre ◽  
Marcelo A. Pavanello
Keyword(s):  
Numerical Simulations ◽  
Analytical Model ◽  
Drain Current ◽  
Channel Length ◽  
Experimental Results ◽  
Two Dimensional ◽  
Effective Channel

In this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI MOSFETs in comparison to conventional SOI transistors is performed. Experimental results show that GC devices present poorer matching behavior in comparison to conventional SOI counterpart for equal mask channel length, whereas for same effective channel length, almost the same matching behavior. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to validate the modelbased analysis both in linear and saturation regions.

Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

2012 ◽  
Vol 59 (12) ◽  
pp. 3510-3518 ◽  
Author(s):  
Renan Doria Trevisoli ◽  
Rodrigo Trevisoli Doria ◽  
Michelly de Souza ◽  
Samaresh Das ◽  
Isabelle Ferain ◽  
...  
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Drain Current ◽  
Nanowire Transistors

Errata to “Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors” [Dec 12 3510-3518]

2016 ◽  
Vol 63 (1) ◽  
pp. 527-527
Author(s):  
Renan Trevisoli ◽  
Rodrigo Trevisoli Doria ◽  
Michelly de Souza ◽  
Samaresh Das ◽  
Isabelle Ferain ◽  
...  
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Drain Current ◽  
Nanowire Transistors

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

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