Analysis of fast and slow responses in AC conductance curves for p-type SiC MOS capacitors

We have investigated the distribution of oxide traps and interface traps in 4H Silicon Carbide MOS devices. The density of interface traps, Dit, was characterized using standard C-V techniques on capacitors and charge pumping on MOSFETs. The number of oxide traps, NOT, was then calculated by measuring the flatband voltage VFB in p-type MOS capacitors. The amount that the measured flatband voltage shifts from ideal, minus the contributions due to the number of filled interface traps Nit, gives an estimate for the number of oxide charges present. We found Dit to be in the low 1011cm−2eV−1 range in midgap and approaching 1012 −1013cm−2eV−1 near the band edges. This corresponds to an Nit of roughly 2.5 ⋅1011cm−2 for a typical capacitor in flatband at room temperature. This data combined with measurements of VFB indicates the presence of roughly 1.3 ⋅1012cm−2 positive NOT charges in the oxide near the interface for our samples.

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Comparison of Electrical Behavior of GaN-Based MOS Structures Obtained by Different PECVD Process

Materials Science Forum ◽

10.4028/www.scientific.net/msf.711.228 ◽

2012 ◽

Vol 711 ◽

pp. 228-232

Author(s):

Elias Al Alam ◽

Ignasi Cortés ◽

T. Begou ◽

Antoine Goullet ◽

Frederique Morancho ◽

...

Keyword(s):

Surface Preparation ◽

Thin Film Deposition ◽

Film Deposition ◽

Plasma Oxidation ◽

Interface Quality ◽

Mos Capacitors ◽

Dielectric Thin Film ◽

P Type ◽

Mos Structures ◽

Uv Ozone

MOS SiO2/GaN structures were fabricated with different surface preparation and different PECVD processes for the dielectric thin film deposition (ECR-PECVD and ICP-PECVD in continuous and pulsed modes). On the basis of C-V curves, the surface preparation steps, involving chemical etching with BOE, UV-Ozone oxidation and oxygen plasma oxidation, were compared in terms of resulting effective charge and interface trap density. A good SiO2/GaN interface quality was achieved for N-type MOS capacitances obtained both with continuousICPPECVD and ECR-PECVD deposition of the SiO2 dielectric. However, the interface quality is greatly reduced for MOS capacitors fabricated on P-type GaN.

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Fabrication of 4H-SiC p-Channel MOSFET with High Channel Mobility

Materials Science Forum ◽

10.4028/www.scientific.net/msf.527-529.1301 ◽

2006 ◽

Vol 527-529 ◽

pp. 1301-1304

Author(s):

Mitsuo Okamoto ◽

Mieko Tanaka ◽

Tsutomu Yatsuo ◽

Kenji Fukuda

Keyword(s):

Valence Band ◽

Oxidation Process ◽

Gate Oxide ◽

Interface States ◽

Wet Oxidation ◽

Mos Capacitors ◽

Channel Mobility ◽

Dry Oxidation ◽

Low Threshold ◽

P Type

We have fabricated inversion-type p-channel MOSFETs on 4H-SiC substrates. In this paper, influences of gate oxidation process on the properties of p-channel MOSFETs were investigated. The gate oxide was formed under these three conditions: (i) dry oxidation, (ii) dry oxidation following wet re-oxidation, and (iii) wet oxidation. The C-V measurements of p-type 4H-SiC MOS capacitors revealed that wet oxidation process reduced the interface states near the valence band. The p-channel MOSFET with low interface states near the valence band indicated low threshold voltage (Vth), high field effect channel mobility (μFE) and low subthreshold swing (S). We obtained 4H-SiC p-channel MOSFET with high μFE of 15.6cm2/Vs by using wet oxidation as gate oxidation process.

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