Fabrication of 4H-SiC p-Channel MOSFET with High Channel Mobility

2006 ◽  
Vol 527-529 ◽  
pp. 1301-1304
Author(s):  
Mitsuo Okamoto ◽  
Mieko Tanaka ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda
Keyword(s):  
Valence Band ◽  
Oxidation Process ◽  
Gate Oxide ◽  
Interface States ◽  
Wet Oxidation ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Dry Oxidation ◽  
Low Threshold ◽  
P Type

We have fabricated inversion-type p-channel MOSFETs on 4H-SiC substrates. In this paper, influences of gate oxidation process on the properties of p-channel MOSFETs were investigated. The gate oxide was formed under these three conditions: (i) dry oxidation, (ii) dry oxidation following wet re-oxidation, and (iii) wet oxidation. The C-V measurements of p-type 4H-SiC MOS capacitors revealed that wet oxidation process reduced the interface states near the valence band. The p-channel MOSFET with low interface states near the valence band indicated low threshold voltage (Vth), high field effect channel mobility (μFE) and low subthreshold swing (S). We obtained 4H-SiC p-channel MOSFET with high μFE of 15.6cm2/Vs by using wet oxidation as gate oxidation process.

Temperature dependences of channel mobility and threshold voltage in 4H- and 6H-SiC MOSFETs

2000 ◽  
Vol 640 ◽  
Author(s):  
S. Harada ◽  
R. Kosugi ◽  
J. Senzaki ◽  
S. Suzuki ◽  
W. J. Cho ◽  
...  
Keyword(s):  
Conduction Band ◽  
Threshold Voltage ◽  
Interface States ◽  
Wet Oxidation ◽  
Oxidation Condition ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Mos Structure ◽  
Temperature Dependences ◽  
P Type

ABSTRACTWe have investigated the effect of polytype and oxidation condition on the temperature dependence of channel mobility and threshold voltage in 4H- and 6H-SiC MOSFETs. The behaviors of the channel mobility are apparently different for 4H- and 6H-SiC MOSFETs. In contrast to the polytype effect, dry and wet oxidation samples have almost similar channel mobilities. The variation of the threshold voltage with temperature is proportional to the number of the interface states near the conduction band extracted from n-type MOS capacitors. Therefore, we argue that the distribution of the interface states near the conduction band in p-type SiC MOS structure can be represented by that in n-type SiC MOS structure. Although the oxidation condition varies the distribution of the interface states in the energy range between 0.2 and 0.4 eV from the conduction band, it has little influence on the channel mobility.

Fabrication of MOS Capacitors by Wet Oxidation of p-Type 4H-SiC Preamorphized by Nitrogen Ion Implantation

2007 ◽  
Vol 556-557 ◽  
pp. 651-654 ◽  
Author(s):  
Yasuto Hijikata ◽  
Sadafumi Yoshida ◽  
Francesco Moscatelli ◽  
Antonella Poggi ◽  
Sandro Solmi ◽  
...  
Keyword(s):  
Interface State ◽  
State Density ◽  
Flat Band ◽  
High Dose ◽  
Wet Oxidation ◽  
High Concentration ◽  
Mos Capacitors ◽  
Dry Oxidation ◽  
Nitrogen Ion ◽  
P Type

4H-SiC p-type MOS capacitors fabricated by wet oxidation of SiC preamorphized by nitrogen ion (N+) implantation have been investigated. The oxidation rate of the SiC layer preamorphized by high-dose N+ was much larger than that of crystalline SiC, allowing us to reduce the fabrication time of SiC MOS devices. We found that the presence of the surface amorphous SiC layer before the oxidation process did not influence the interface state density in MOS capacitors. Moreover, the shift of the flat-band voltage is not correlated to the amount of nitrogen in the oxide. On the contrary the density of interface states near the valence band edge increased according with the high concentration of the implanted N at the oxide–SiC interface, as in the case of dry oxidation reported by Ciobanu et al. The generation of positive charges due to the nitrogen embedded inside the oxide layer was smaller compared with dry oxidation. We discuss the difference between wet and dry oxidation for MOS capacitors fabricated with N+ implantation.

Process Optimisation for 4H-SiC MOSFET Applications

2006 ◽  
Vol 527-529 ◽  
pp. 1051-1054 ◽  
Author(s):  
Caroline Blanc ◽  
Dominique Tournier ◽  
Phillippe Godignon ◽  
D.J. Brink ◽  
Véronique Soulière ◽  
...  
Keyword(s):  
Field Effect ◽  
Oxidation Process ◽  
Gate Oxide ◽  
Process Optimisation ◽  
Field Effect Mobility ◽  
Oxide Formation ◽  
Step Procedure ◽  
P Type ◽  
Peak Value ◽  
Gas Precursor

We report on 4H-SiC MOSFET devices implemented on p-type <11-20>-oriented epitaxial layers, using a two-step procedure for gate oxide formation. First is a thin, dry, thermal SiO2 layer grown at 1050°C for 1 hour. Next, is a thick (50 nm) layer of complementary oxide deposited by PECVD using TEOS as gas precursor. With respect to the standard thermal oxidation process, this results in much improvement of the field effect mobility. For the best samples, we find a peak value in the range of 330 cm2/Vs while, on the full wafer, an average mobility of about 160 cm2/Vs is found. Up to now, this is one of the best results ever reported for 4H-SiC MOSFETs.

Electrical Properties of High-K LaLuO3 Gate Oxide for SOI MOSFETs

2011 ◽  
Vol 276 ◽  
pp. 87-93
Author(s):  
Y.Y. Gomeniuk ◽  
Y.V. Gomeniuk ◽  
A. Nazarov ◽  
P.K. Hurley ◽  
Karim Cherkaoui ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Interface State ◽  
Channel Length ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Threshold Voltages

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

Comparison of channel mobility and oxide properties of MOSFET devices on Si-face (0001) and A-face (11-20) 4H-SiC

2014 ◽  
Vol 1693 ◽  
Author(s):  
Daniel J. Lichtenwalner ◽  
Lin Cheng ◽  
Scott Allen ◽  
John W. Palmour ◽  
Aivars Lelis ◽  
...  
Keyword(s):  
Valence Band ◽  
Barrier Height ◽  
Field Effect ◽  
Phonon Scattering ◽  
Electron Tunneling ◽  
Negative Temperature ◽  
Field Effect Mobility ◽  
Channel Mobility ◽  
P Type ◽  
And Control

ABSTRACTIn this report we present results comparing lateral MOSFET properties of devices fabricated on Si-face (0001) and A-face (11-20) 4H-SiC, with nitric oxide passivation anneals. We observe a field-effect mobility of 33 cm2/V.s on p-type 5×1015 doped Si-face. These devices have a peak field-effect mobility which increases with temperature, indicative of a channel mobility limited by coulomb scattering. On 1×1016 p-type A-face SiC, the peak channel mobility is observed to be 80 cm2/V.s, with a negative temperature dependence, indicating that phonon-scattering effects dominate, with a much lower density of shallow acceptor traps. This > 2x higher channel mobility would result in a substantial decrease in on-resistance, hence lower power losses, for 4H-SiC power MOSFETs with voltage ratings below 2 kV. However, MOS C-V and gate leakage measurements indicate very different oxide and interface quality on each SiC face. For example, the Fowler-Nordheim (FN) conduction-band (CB) barrier height for electron tunneling at the SiO2/SiC interface is 2.8 eV on Si-face SiC, while it is 2.5 eV or less on A-face SiC. For the valence-band side, the effective FN barrier height at the valence-band (VB) side of only 1.6 eV on A-face SiC, while the VB barrier height is about 3.1 eV on Si-face SiC. Moreover, C-V of the MOS gate on A-face indicates the presence of a high-density of deep hole traps. It is apparent that oxides on alternative crystal faces, very promising in terms of channel mobility, require further study for complete understanding and control of the interface properties.

Design and Process Issues for Silicon Carbide Power DiMOSFETS

2000 ◽  
Vol 640 ◽  
Author(s):  
Sei-Hyung Ryu ◽  
Anant K. Agarwal ◽  
Nelson S. Saks ◽  
Mrinal K. Das ◽  
Lori A. Lipkin ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Structure ◽  
Channel Mobility ◽  
Power Mosfets ◽  
Buried Channel ◽  
P Type ◽  
Very High ◽  
Effective Channel

ABSTRACTThis paper discusses the design and process issues of high voltage power DiMOSFETs (Double implanted MOSFETs) in 4H-silicon carbide (SiC). Since Critical Field (EC) in 4H-SiC is very high (10X higher than that of a Si), special care is needed to protect the gate oxide. 2D device simulation tool was used to determine the optimal JFET gap, which provides adequate gate oxide protection as well as a reasonable JFET resistance. The other issue in 4H-SiC DiMOSFETs is extremely low effective channel mobility (μeff) in the implanted p-well regions. NO anneal of the gate oxide and buried channel structure are used for increasing μeff. NO anneal, which was reported to be very effective in increasing the μeff of SiC MOSFETS in p-type epilayers, did not produce reasonable μeff of SiC MOSFETs in the implanted p-well. Buried channel (BC) structure with 2.7×1012 cm−2 charge in the channel showed high μeff utilizing bulk buried channel, but resulted in a normally-on device. However, it was shown that by controlling the charge in the BC layer, a normally off device with high μeff can be produced. A 3.3 mm × 3.3 mm DiMOSFET with BC structure showed a drain current of 10 A, which is the highest current reported in SiC power MOSFETs to date, at a forward drop of 4.4 V with a gate bias of only 2.5 V.

Fabrication of MOS Capacitors by Wet Oxidation of p-Type 4H-SiC Preamorphized by Nitrogen Ion Implantation

2007 ◽  
pp. 651-654
Author(s):  
Yasuto Hijikata ◽  
Sadafumi Yoshida ◽  
Francesco Moscatelli ◽  
Antonella Poggi ◽  
Sandro Solmi ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Wet Oxidation ◽  
Mos Capacitors ◽  
Nitrogen Ion Implantation ◽  
Nitrogen Ion ◽  
P Type

Interface States in 4H- and 6H-SiC MOS Capacitors: A Comparative Study between Conductance Spectroscopy and Thermal Dielectric Relaxation Current Technique

2009 ◽  
Vol 615-617 ◽  
pp. 497-500 ◽  
Author(s):  
Lars S. Løvlie ◽  
Ioana Pintilie ◽  
S. Kumar C.P. ◽  
Ulrike Grossner ◽  
Bengt Gunnar Svensson ◽  
...  
Keyword(s):  
Comparative Study ◽  
Dielectric Relaxation ◽  
Cross Section ◽  
Capture Cross Section ◽  
Interface States ◽  
Conduction Band Edge ◽  
Capture Cross ◽  
Mos Capacitors ◽  
Dry Oxidation ◽  
Good Agreement

The purpose of this work is to compare the density of shallow interface states (Dit) at the interface of SiO2/SiC MOS capacitors as deducted by the conductance spectroscopy (CS) and thermally dielectric relaxation current (TDRC) techniques. Both capacitors of 4H- and 6H-SiC (n-type) are investigated, and both ordinary dry oxidation and an improved industrial procedure have been employed. The two techniques are found to give rather good agreement for interface states located ≥0.3 eV below the conduction band edge (Ec) while for more shallow states vastly different distributions of Dit are obtained. Different reasons for these contradictory results are discussed, such as strong temperature and energy dependence of the capture cross section of the shallow interface states.

4H-SiC MOS Capacitors and MOSFET Fabrication with Gate Oxidation at 1400°C

2014 ◽  
Vol 778-780 ◽  
pp. 607-610 ◽  
Author(s):  
Harsh Naik ◽  
T. Paul Chow
Keyword(s):  
High Temperature ◽  
Oxidation Process ◽  
Annealing Process ◽  
Mos Capacitors ◽  
Hall Measurements ◽  
Dry Oxidation

This paper compares the performance of 4H-SiC MOS capacitors and MOSFETs made using the conventional NO annealing process and a high-temperature (1400°C) dry oxidation process. Through extensive C-V, G-ω, I-V and Hall measurements, the limitations of both the processes are discussed.

Evaluation of 4H-SiC Carbon Face Gate Oxide Reliability

2011 ◽  
Vol 679-680 ◽  
pp. 354-357
Author(s):  
Jody Fronheiser ◽  
Aveek Chatterjee ◽  
Ulrike Grossner ◽  
Kevin Matocha ◽  
Vinayak Tilak ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Inversion Layer ◽  
Gate Oxide ◽  
Dielectric Strength ◽  
Time To Failure ◽  
Research Groups ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability

The gate oxide reliability and channel mobility of carbon face (000-1) 4H Silicon Carbide (SiC) MOSFETs are investigated. Several gate oxidation processes including dry oxygen, pyrogenic steam, and nitrided oxides were investigated utilizing MOS capacitors for time dependent dielectric breakdown (TDDB), dielectric field strength, and MOSFETs for inversion layer mobility measurements. The results show the C-face can achieve reliability similar to the Si-face, however this is highly dependent on the gate oxide process. The reliability is inversely related to the field effect mobility where other research groups report that pyrogenic steam yields the highest electron mobility while this work shows it has weakest oxide in terms of dielectric strength and shortest time to failure.

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