An Adaptive Gamification Learning Approach on Digital Logic Gates: LogIO

Author(s):  
J. O. Torio ◽  
R. T. Bigueras ◽  
D. E. Maligat Jr. ◽  
M.C. A. Arispe ◽  
J. S.Dela Cruz
Author(s):  
JO Torio ◽  
R T Bigueras ◽  
D E Maligat ◽  
M A Arispe ◽  
J S Dela Cruz

2016 ◽  
Vol E99.C (2) ◽  
pp. 285-292 ◽  
Author(s):  
Tran THI THU HUONG ◽  
Hiroshi SHIMADA ◽  
Yoshinao MIZUGAKI

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Charles El Helou ◽  
Philip R. Buskohl ◽  
Christopher E. Tabor ◽  
Ryan L. Harne

AbstractIntegrated circuits utilize networked logic gates to compute Boolean logic operations that are the foundation of modern computation and electronics. With the emergence of flexible electronic materials and devices, an opportunity exists to formulate digital logic from compliant, conductive materials. Here, we introduce a general method of leveraging cellular, mechanical metamaterials composed of conductive polymers to realize all digital logic gates and gate assemblies. We establish a method for applying conductive polymer networks to metamaterial constituents and correlate mechanical buckling modes with network connectivity. With this foundation, each of the conventional logic gates is realized in an equivalent mechanical metamaterial, leading to soft, conductive matter that thinks about applied mechanical stress. These findings may advance the growing fields of soft robotics and smart mechanical matter, and may be leveraged across length scales and physics.


2018 ◽  
Vol 7 (2.23) ◽  
pp. 464
Author(s):  
Angshuman Khan ◽  
Sudip Halder ◽  
Shubhajit Pal

This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.  


2009 ◽  
Vol 21 (19) ◽  
pp. 1468-1470 ◽  
Author(s):  
M.R. Uddin ◽  
J.S. Lim ◽  
Y.D. Jeong ◽  
Y.H. Won

2003 ◽  
Vol 14 (2) ◽  
pp. 188-191 ◽  
Author(s):  
Seung-Beck Lee ◽  
Gregory D Hutchinson ◽  
David A Williams ◽  
David G Hasko ◽  
Haroon Ahmed
Keyword(s):  

2009 ◽  
Vol 30 (4) ◽  
Author(s):  
Bei Li ◽  
Muhammad Irfan Memon ◽  
Gabor Mezosi ◽  
Zhuoran Wang ◽  
Marc Sorel ◽  
...  

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