scholarly journals Study on the Impact of Lead Sidewall Solder Coverage and Corner Lead Size on Joint Reliability

Author(s):  
Jefferson Talledo

Solder joint reliability is very important to ensure that an integrated circuit (IC) semiconductor package is functional within its intended life span as the solder joint establishes electrical connection between the IC and the printed circuit board (PCB). Solder fatigue failure or crack under thermal cycling is one of the common problems with board-mounted packages. There are several factors or package characteristics that have impact on solder fatigue life like package size and material properties of the package components. This paper presents a thermo-mechanical modeling of a leadframe-based semiconductor package to study the impact of lead sidewall solder coverage and corner lead size on the solder joint reliability. Finite element analysis (FEA) technique was used to calculate the solder life considering 50% and 100% package lead sidewall solder coverage as well as smaller and larger critical corner leads of the package. The results of the analysis showed that higher lead sidewall solder coverage and larger lead could significantly increase solder life. Therefore, ensuring lead sidewall solder wettability to have higher solder coverage is beneficial. The study also reveals that packages with side wettable flanks are not only enabling high speed automated optical inspection required for the automotive industry, but they are also providing improved solder joint reliability.

Author(s):  
Jefferson Talledo

Leadframe-based packages are commonly used for semiconductor power devices. With these packages, heat dissipation is much better compared with laminate substrated-based packages. However, the solder joint reliability requirement under thermal cycling condition is also higher and this is what makes the development of a power package challenging. One of the usual requirements from customers is that there should be no solder joint failure up to 2,000 thermal cycles. This paper presents the thermomechanical simulation of a power leadframe package that was conducted to improve its solder joint reliability. Board level solder joint cycle life was predicted using finite element analysis and the result was validated with actual solder life result from board level reliability evaluation. Since available solder prediction equation was for the characteristic life (63.2% accumulative failure), using the normalized characteristic life was implemented for predicting the number of cycles to first failure of the solder joint connection and the approach showed good agreement with the actual result. Results also indicated that the choice of epoxy mold material and the type of PCB (printed circuit board) have a significant contribution to the solder joint reliability performance.


Author(s):  
Roy W. Knight ◽  
Yasser Elkady ◽  
Jeffrey C. Suhling ◽  
Pradeep Lall

The thermal performance of Ball Grid Array packages depends upon many parameters including die size, use of thermal balls, number of perimeter balls, use of underfill, and printed circuit board heat spreader and thermal via design. Thermal cycling can affect the integrity of thermal paths in and around the BGA as a result of the cracking of solder balls and delamination of the package, including at underfill interfaces. In this study, the impact of thermal cycling on the thermal performance of BGA’s was investigated and quantified. A number of test boards which included a range of the parameters cited above were experimentally examined. A baseline thermal resistance was measured for each case, which was verified with numerical thermal modeling. The boards were then subjected to thermal cycling from −40°C to 125°C. Every 250 cycles the thermal performance was measured. Packages expected to be least reliable (with large die and no underfill), showed an increase in thermal resistance after 750 thermal cycles. Further increases in thermal resistance were observed with continuous thermal cycling until solder joint failure occurred at 1250 cycles, preventing additional measurements. Finite element analysis identified critical thermal and perimeter solder balls as the most likely sites for cracking. Boards were cross-sectioned and examined for solder joint cracks and delamination to identify the cause for the observed increases in thermal resistance. Cracking was found in the critical thermal and perimeter solder balls.


Author(s):  
Kuldip Johal ◽  
Rick Nichols

Soldering on ball grid arrays (BGAs) and dense circuit features is standard practice in the microelectronics industry. Key to the success of this operation is solder joint reliability (SJR). The evaluation of solder joint reliability can be satisfied by high speed shear testing (HSS). HSS testing in combination with representative test vehicles are tools that can be used to gain statistical data in order to evaluate the impact of controlled testing. During such a round of controlled testing in the context of a palladium phosphor ENEPIG process, it was observed that the palladium initiation speed and IMC may be related to HSS results. The focus of this paper is not targeting all the optimizations that can lead to high end reliability performance for solderability. This paper will strive to convey steps that are available to all fabricators to maximize High Speed Shear results (HSS). In this paper, it will be shown that soldermask related pinholes can be overcome by implementing a reduction assisted immersion gold bath. This section will also culminate in SJR improvements and stability. The prevention of pin holes is a complicated multifaceted problem. This paper will address the notion that, if pinholes are evident, an enhanced immersion gold bath can be used to overcome serious corrosion. Disturbances in the nickel deposit can be weaknesses that are open for unusual locally aggressive atom exchange between the gold and the nickel that will result is hyper-corrosion. A reduction assisted gold bath is able to mask such areas with controlled deposition. This paper will demonstrate the effectiveness of the optimized, purpose designed, gold bath in overcoming pinhole related corrosion whilst simultaneously scrutinizing the ability of the reduction assisted gold bath to maintain or enhance the reliability expectations that are benchmarked by traditional immersion gold alternatives. During studies it has also been observed that processing is also instrumental in assuring maximum soldering reliability. Whilst rinsing is an accepted procedure, the degree and method of rinsing is often a controversial topic. This is especially true of vertical processes where fluid exchange is replaced by soaking, or in other words agitation neutral, volume related dilution. Environmentally aware practices err on the side of minimal water consumption. This is a requirement that is influenced or selectively amplified by geographical locations. This technical paper will demonstrate that the palladium initiation is crucial if maximum SJR is to be achieved. This experience was gained in association with a significant OEM. Electrochemical and advanced optical techniques will be used to demonstrate that the SJR in terms of HSS can be correlated to palladium initiation and resultant IMC formations. In summary process adjustments can be employed to improve soldering performance and repetition. An optimized reduction assisted gold bath will come together with processing optimizations to provide a data driven overview to convince fabricators that enhancements to their everyday processes exist and can be implemented by drop in solutions. The data that is included should be as interesting to the automotive industry as it is to the emerging substrate like panel industry (SLP).


Author(s):  
M. Niessner ◽  
G. Haubner ◽  
W. Hartner ◽  
S. Pahlke

A DfR (Design for Reliability) approach which is systematically based on simulation, sensitivity analysis and experimental validation is applied for identifying, understanding and controlling the key factors which determine the solder joint reliability of eWLB (Embedded Wafer Level Ball Grid Array) packages that carry embedded 77 GHz dies and sit on hybrid PCB (Printed Circuit Board) stacks. The hybrid stack investigated in this work is characteristic to automotive RADAR (Radio Detection And Ranging) applications and consists of one low-loss RF (Radio Frequency) layer and several FR4 layers. In line with previous work [1], the mechanical material properties of the low-loss RF laminate material are found to be the key factor. Simulation is used to systematically screen for mechanical properties which are favorable for achieving a high solder joint reliability on the unconstrained PCBs used for standardized solder joint reliability testing. A simplified virtual assessment of PCBs constrained by the mounting in system module housings is done. Both simulation and experimental results show that RF laminate materials with low Young’s modulus are the class of materials which allows for the highest solder joint reliability for all the conditions investigated in this study.


Author(s):  
John Lau ◽  
Yida Zou ◽  
Sergio Camerlo

The creep analyses of solder-bumped wafer-level chip-scale package (WLCSP) on printed circuit board (PCB) subjected to temperature cycling loading are presented. Emphasis is placed on the effects of PCB thickness on the solder joint reliability of the WLCSP assembly. Also, the effects of crack-length on the crack tip characteristics such as the J-integral in the WLCSP solder joint are studied by the fracture mechanics method. Finally, the effects of voids on the crack growth in the WLCSP solder joint are investigated.


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