scholarly journals A High Bandwidth-Power Efficiency, Low THD2,3 Driver Amplifier with Dual-Loop Active Frequency Compensation for High-Speed Applications

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2311
Author(s):  
Ximing Fu ◽  
Kamal El-Sankary ◽  
Yadong Yin

This paper presents a driver amplifier with high bandwidth-power efficiency, high capacitor-driving capacity, and low total harmonic distortion (THD). One complementary differential pair composed of self-cascode transistors is incorporated to obtain a full input voltage swing. Flipped voltage follower (FVF) buffers are applied as second stage to drive the last class-AB output stage. Moreover, a dual-loop active-feedback frequency compensation (DLAFC) is presented, which can stabilize the proposed multistage amplifier and keep the dominant pole on high frequency to obtain high-frequency total harmonic distortion (THD) suppression. To achieve a low-frequency phase margin protection (PMP), one left half-plane (LHP) zero is introduced to compensate for the nondominant pole caused by the load capacitor. Meanwhile, two high-frequency LHP zeros are injected to achieve high-frequency phase margin boosting (PMB) and reduce the amplifier’s settling time and integration area. This proposed amplifier is implemented in a standard DBH 0.18 μm 5 V CMOS process, and it achieves over 115-dB DC gain, 150–300 MHz GBW under 0–100 p load capacitors, ultra-high THD2,3 suppression ranges from 100 kHz to 10 MHz under 1–2 V output swing, and over 250 V/μs average slew rate, by only dissipating 12.5 mW at 5 V power supply.

2012 ◽  
Vol 614-615 ◽  
pp. 1539-1546
Author(s):  
Muhamad Fairus Hamid ◽  
Norazlan Hashim ◽  
Ahmad Farid Abidin

This paper presents an analysis and improvement of self-oscillation electronic ballast for local emergency light. The improvement circuit has been presented by replacing the original BJTs with MOSFETs as a switching device. Also, 555-timer has been used to drive the MOSFETs instead of the ballast feedback in the original circuit. This electronic ballast start and regulate fluorescent lamps by converting a DC supply to high ignition AC voltage by a rectifier circuit with switching frequency in the range of 20 kHz -1MHz. Operation at high frequency has two advantages; an improved efficiency and elimination of flickering in the lamps. The simulation has been done by using PSIM Simulink software and its results have been compared with experimental results. The results shows that by using MOSFETs as a switching device, the Total Harmonic Distortion (THD) has been reduced and the brightness of lamp tube has been increased greatly.


2011 ◽  
Vol 403-408 ◽  
pp. 3600-3607
Author(s):  
S. Selvaperumal ◽  
C.Christober Asir Rajan

This paper presents 250W, 20 KHz LCL resonant inverter having Efficiencies greater than 95% were obtained down to resistive loads of 50%. Efficiencies greater than 80% were obtained at significantly reduced loads (11%). Operation above resonance was utilized to increase the efficiency and maintain zero voltage switching (ZVS) for varied loads. Total harmonic distortion (THD) of less than 8% was achieved for all resistive loads. The above results were obtained from evaluation version of PSIM also used to model the LCL topology for varied loads and LCL configurations. A LCL Resonant Inverter is proposed for applications in high frequency distributed AC power systems.


Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8476
Author(s):  
Yuxuan Tang ◽  
Yulang Feng ◽  
He Hu ◽  
Cheng Fang ◽  
Hao Deng ◽  
...  

This paper presents a wideband low-noise amplifier (LNA) front-end with noise and distortion cancellation for high-frequency ultrasound transducers. The LNA employs a resistive shunt-feedback structure with a feedforward noise-canceling technique to accomplish both wideband impedance matching and low noise performance. A complementary CMOS topology was also developed to cancel out the second-order harmonic distortion and enhance the amplifier linearity. A high-frequency ultrasound (HFUS) and photoacoustic (PA) imaging front-end, including the proposed LNA and a variable gain amplifier (VGA), was designed and fabricated in a 180 nm CMOS process. At 80 MHz, the front-end achieves an input-referred noise density of 1.36 nV/sqrt (Hz), an input return loss (S11) of better than −16 dB, a voltage gain of 37 dB, and a total harmonic distortion (THD) of −55 dBc while dissipating a power of 37 mW, leading to a noise efficiency factor (NEF) of 2.66.


Author(s):  
He Wang ◽  
Chengwen Wang ◽  
Long Quan ◽  
Guofang Gong ◽  
Wenjing Li

The present study is focused on a novel method for the acquisition of high-frequency sinusoidal vibration waveform with electro-hydraulic vibration exciter. A rotary valve controlled electro-hydraulic vibration exciter is proposed to make it easier to obtain high vibration frequency than the conventional servo valve controlled counterpart. Three common used offices are taken into consideration: rectangular orifice, triangular orifice, and semicircular orifice. Analytical solution to orifice design of shape and axial length is suggested for the accurate control of vibration waveform. Harmonic theory borrowed from electronic technology is used as an evaluation index for the shape of vibration waveform. The orifice shape design decision is made according to the total harmonic distortion of vibration waveform. The nonlinear differential equation which models vibration waveform is established. The orifice axial length is designed according to the supply pressure, vibration frequency, and amplitude. Both theoretical and experimental results show that rectangular orifice is desirable for high-frequency sinusoidal vibration waveforms. With the orifice design solution, the proposed vibration exciter can output the vibration waveform with total harmonic distortion of less than 1% as compared with sinusoidal waveform and maximum error of 5% as compared with experimental value at vibration frequency of higher than 100 Hz, and greatly extend the frequency bandwidth when sinusoidal vibration waveform is required.


2017 ◽  
Vol 26 (11) ◽  
pp. 1750176 ◽  
Author(s):  
Yani Li ◽  
Zhangming Zhu ◽  
Yintang Yang ◽  
Yadong Sun ◽  
Xu Wang

To improve conversion efficiency and output quality of the energy harvester, a novel interface circuit with composite maximum power point tracking (MPPT) in energy harvesting applications is proposed in this paper. By using the ultra-low-voltage multiplier with digital control and simple one-cycle variable frequency technique, the converter realizes fast power tracking and high conversion efficiency, and minimizes the power consumption and harmonics, thereby obtaining high tracking precise and low total harmonic distortion (THD). Implemented in 65-nm CMOS process, this converter achieves 85.9% peak power efficiency with dc output voltage of 1.6[Formula: see text]V. The peak tracking efficiency and THD are 99.2% and 1.3%, respectively. The peak output power is 18.31[Formula: see text][Formula: see text]W, and the power loss of the entire converter is only 16.53[Formula: see text][Formula: see text]W.


2021 ◽  
Author(s):  
Alon Kuperman

The paper reveals analytical expressions linking the coefficients of PI controller, typically employed as voltage loop compensator of power factor correction rectifiers (PFCR), with two major performance merits (namely, total harmonic distortion (THD) of grid-side current and DC-link voltage deviation upon sudden load increase) and DC link capacitance to rated power ratio. The proposed methodology allows to concretize the commonly used "8–10Hz crossover frequency, 45 degree–70 degree phase margin" rule-of-thumb, typically utilized in application notes of commercial PFC controllers. Relations between voltage loop gain crossover frequency and phase margin as well as settling time of DC-link voltage response to a step load increase to the above mentioned performance merits are also derived in the paper. Provided design guidelines allow to precisely achieve desired values of the two mentioned performance merits and indicate the feasible range of possible DC link capacitance values. Proposed quantitative design guidelines are well-supported by experiments.


Author(s):  
Gurumurthy Komanaplli ◽  
Neeta Pandey ◽  
Rajeshwari Pandey

In this paper a new, operational transresistance amplifier (OTRA) based, third order quadrature oscillator (QO) is presented. The proposed structure forms a closed loop using a high pass filter and differentiator. All the resistors employed in the circuit can be implemented using matched transistors operating in linear region thereby making the proposed structure fully integrated and electronically tunable. The effect of non-idealities of OTRA has been analyzed which suggests that for high frequency applications self-compensation can be used. Workability of the proposed QO is verified through SPICE simulations using 0.18μm AGILENT CMOS process parameters. Total harmonic distortion (THD) for the proposed QO is found to be less than 2.5%.The sensitivity, phasenoise analysis is also discussed for the proposed structure.


2014 ◽  
Vol 2014 ◽  
pp. 1-5 ◽  
Author(s):  
Rajeshwari Pandey ◽  
Neeta Pandey ◽  
Gurumurthy Komanapalli ◽  
Rashika Anurag

Two topologies of operational transresistance (OTRA) based third order quadrature oscillators (QO) are proposed in this paper. The proposed oscillators are designed using a combination of lossy and lossless integrators. The proposed topologies can be made fully integrated by implementing the resistors using matched transistors operating in linear region, which also facilitates electronic tuning of oscillation frequency. The nonideality analysis of the circuit is also given and for high frequency applications self-compensation can be used. Workability of the proposed QOs is verified through PSPICE simulations using 0.5 μm AGILENT CMOS process parameters. The total harmonic distortion (THD) for both the QO designs is found to be less than 1%.


2021 ◽  
Author(s):  
Alon Kuperman

The paper reveals analytical expressions linking the coefficients of PI controller, typically employed as voltage loop compensator of power factor correction rectifiers (PFCR), with two major performance merits (namely, total harmonic distortion (THD) of grid-side current and DC-link voltage deviation upon sudden load increase) and DC link capacitance to rated power ratio. The proposed methodology allows to concretize the commonly used "8–10Hz crossover frequency, 45 degree–70 degree phase margin" rule-of-thumb, typically utilized in application notes of commercial PFC controllers. Relations between voltage loop gain crossover frequency and phase margin as well as settling time of DC-link voltage response to a step load increase to the above mentioned performance merits are also derived in the paper. Provided design guidelines allow to precisely achieve desired values of the two mentioned performance merits and indicate the feasible range of possible DC link capacitance values. Proposed quantitative design guidelines are well-supported by experiments.


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