scholarly journals In-Pixel CTIA & Readout Circuitry for an Active CMOS Image Sensor

2021 ◽  
Vol 16 ◽  
pp. 626-632
Author(s):  
Aicha Menssouri ◽  
Karim El Khadiri ◽  
Ahmed Tahiri
Keyword(s):  
Supply Voltage ◽  
Cmos Image Sensor ◽  
Cmos Technology ◽  
Image Sensor ◽  
Transimpedance Amplifier ◽  
Phase Margin ◽  
Prior Work ◽  
Gain Margin ◽  
Pixel Circuit ◽  
Pixel Output

This work aims to design and simulate an in-pixel Capacitive Transimpedance Amplifier (CTIA) and peripheral circuitry that ensures pixel reading. Each pixel circuit is composed of four transistors using 90nm CMOS technology with a supply voltage of 1.8 V and is part of an array of pixels that make up a CMOS image sensor with peripheral circuitry. Pixel output is sent to a delta difference sampling (DDS) circuit to filter reset voltages. The Gain Margin achieved for the in-pixel CTIA is 44dB and 91dB for the Phase Margin. We also present measured pixel parameters and give a comparison with prior work. The timing and readout circuitry is also described.

Color mixing improvement of CMOS image sensor with air-gap-guard ring in deep-submicrometer CMOS technology

2005 ◽  
Vol 26 (5) ◽  
pp. 301-303 ◽  
Author(s):  
T.H. Hsu ◽  
Y.K. Fang ◽  
D.N. Yaung ◽  
S.G. Wuu ◽  
H.C. Chien ◽  
...  
Keyword(s):  
Cmos Image Sensor ◽  
Cmos Technology ◽  
Image Sensor ◽  
Air Gap ◽  
Guard Ring ◽  
Deep Submicrometer ◽  
Color Mixing

scholarly journals A CMOS voltage-mode image sensing system

2021 ◽  
Author(s):  
Jun Long Zhang
Keyword(s):  
Cmos Image Sensor ◽  
Cmos Technology ◽  
Image Sensor ◽  
Electrical Signal ◽  
Image Sensors ◽  
Analog To Digital ◽  
Light Sensing ◽  
Image Sensing ◽  
Cmos Image Sensors ◽  
Pixel Sensors

A CMOS image sensor consists of a light sensing region that converts photonic energy to an electrical signal and a peripheral circuitry that performs signal conditioning and post-processing. This project investgates the principle and design of CMOS active image sensors. The basic concepts and principle of CMOS image sensors are investigated. The advantages of CMOS image sensors over charge-coupled device (CCD) image sensors are presented. Both passive pixel sensors (PPS) and acive pixel sensors (APS) are examined in detail. The noise of CMOS image sensors is investigated and correlated double sampling (CDS) techniques are examined. The design of APS arrays, CDS circuits and 8-bit analog to-digital converters in TSMC-0.18μm 1.8V CMOS technology is presented. The simulation results and layout of the designed CMOS image sensor are presented.

scholarly journals Transimpedance Amplifier for Short-Reach SI-POF Links

1970 ◽  
Vol 3 ◽  
pp. 45-46
Author(s):  
Guillermo Royo ◽  
Cecilia Gimeno ◽  
Carlos Sánchez-Azqueta ◽  
Concepción Aldea ◽  
Santiago Celma
Keyword(s):  
Optical Fiber ◽  
Low Power ◽  
Supply Voltage ◽  
Low Cost ◽  
Cmos Technology ◽  
Transimpedance Amplifier ◽  
Plastic Optical Fiber ◽  
Step Index

This paper presents the design of a low-power lowvoltage transimpedance amplifier for short reach applications through low-cost step index plastic optical fiber. The amplifier has been designed in a 180 nm CMOS technology and dissipates 6 mW from a supply voltage of only 1 V. The design achieves 1.25 Gb/s through 50 m POF and a sensitivity of -20 dBm considering a 10-12 BER.

scholarly journals Design and Analysis of Three-Stage Amplifier for Driving pF-to-nF Capacitive Load Based on Local Q-Factor Control and Cascode Miller Compensation Techniques

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 572 ◽  
Author(s):  
Qi Cheng ◽  
Weimin Li ◽  
Xian Tang ◽  
Jianping Guo
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Step Response ◽  
Phase Margin ◽  
Q Factor ◽  
Physical Size ◽  
Miller Compensation ◽  
Frequency Peak ◽  
Capacitive Load ◽  
Compensation Approach

This paper presents a new frequency compensation approach for three-stage amplifiers driving a pF-to-nF capacitive load. Thanks to the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively, and the physical size of the compensation capacitors is also reduced. A local Q-factor control (LQC) loop is introduced to alter the Q-factor adaptively when loading capacitance CL varies significantly. This LQC loop decides how much damping current should be injected into the corresponding parasitic node to control the Q-factor of the complex-pole pair, which affects the frequency peak at the gain plot and the settling time of the proposed amplifier in the closed-loop step response. Additionally, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Simulated in 0.13-µm CMOS technology, the amplifier is verified to handle a 4-pF-to-1.5-nF (375× drivability) capacitive load with at least 0.88-MHz gain-bandwidth (GBW) product and 42.3° phase margin (PM), while consuming 24.0-µW quiescent power at 1.0-V nominal supply voltage.

A high-efficiency CMOS image sensor with air gap in situ MicroLens (AGML) fabricated by 0.18-/spl mu/m CMOS technology

2005 ◽  
Vol 26 (9) ◽  
pp. 634-636 ◽  
Author(s):  
T.H. Hsu ◽  
Y.K. Fang ◽  
D.N. Yaung ◽  
S.G. Wuu ◽  
H.C. Chien ◽  
...  
Keyword(s):  
High Efficiency ◽  
Cmos Image Sensor ◽  
Cmos Technology ◽  
Image Sensor ◽  
Air Gap

scholarly journals Two-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Fang Tang ◽  
Amine Bermak ◽  
Abbes Amira ◽  
Mohieddine Amor Benammar ◽  
Debiao He ◽  
...  
Keyword(s):  
Power Consumption ◽  
Error Correction ◽  
Cmos Image Sensor ◽  
Cmos Technology ◽  
Image Sensor ◽  
Sar Adc ◽  
Quantization Noise ◽  
Noise Performance ◽  
Chip Area ◽  
Full Resolution

Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR) ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μm CMOS technology. The chip area of the proposed ADC is 7 μm × 500 μm. The measurement results show that the energy efficiency figure-of-merit (FOM) of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k μm2·cycles/sample.

scholarly journals A 250 m Direct Time-of-Flight Ranging System Based on a Synthesis of Sub-Ranging Images and a Vertical Avalanche Photo-Diodes (VAPD) CMOS Image Sensor

Sensors ◽  
2018 ◽  
Vol 18 (11) ◽  
pp. 3642 ◽  
Author(s):  
Yutaka Hirose ◽  
Shinzo Koyama ◽  
Motonori Ishii ◽  
Shigeru Saitou ◽  
Masato Takemoto ◽  
...  
Keyword(s):  
Near Infrared ◽  
Time Of Flight ◽  
Depth Map ◽  
Complementary Metal Oxide Semiconductor ◽  
Laser Pulses ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Pixel Circuit

We have developed a direct time-of-flight (TOF) 250 m ranging Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) based on a 688 × 384 pixels array of vertical avalanche photodiodes (VAPD). Each pixel of the CIS comprises VAPD with a standard four transistor pixel circuit equipped with an analogue capacitor to accumulate or count avalanche pulses. High power near infrared (NIR) short (<50 ns) and repetitive (6 kHz) laser pulses are illuminated through a diffusing optics. By globally gating the VAPD, each pulse is counted in the in-pixel counter enabling extraction of sub-photon level signal. Depth map imaging with a 10 cm lateral resolution is realized from 1 m to 250 m range by synthesizing subranges images of photon counts. Advantages and limitation of an in-pixel circuit are described. The developed CIS is expected to supersede insufficient resolution of the conventional light detection and ranging (LiDAR) systems and the short range of indirect CIS TOF.

scholarly journals A 3.0 Gsymbol/s/lane MIPI C-PHY Receiver with Adaptive Level-Dependent Equalizer for Mobile CMOS Image Sensor

Sensors ◽  
2021 ◽  
Vol 21 (15) ◽  
pp. 5197
Author(s):  
Seokwon Choi ◽  
Changmin Song ◽  
Young-Chan Jang
Keyword(s):  
Duty Cycle ◽  
High Speed ◽  
Supply Voltage ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Cmos Process ◽  
Peak Time ◽  
Time Jitter ◽  
Mobile Industry ◽  
Sensor Interfaces

A 3.0 Gsymbol/s/lane receiver is proposed herein to acquire near-grounded high-speed signals for the mobile industry processor interface (MIPI) C-PHY version 1.1 specification used for CMOS image sensor interfaces. Adaptive level-dependent equalization is also proposed to improve the signal integrity of the high-speed receivers receiving three-level signals. The proposed adaptive level-dependent equalizer (ALDE) is optimized by adjusting the duty cycle ratio of the clock recovered from the received data to 50%. A pre-determined data pattern transmitted from a MIPI C-PHY transmitter is established to perform the adaptive level-dependent equalization. The proposed MIPI C-PHY receiver with three data lanes is implemented using a 65 nm CMOS process with a 1.2 V supply voltage. The power consumption and area of each lane are 4.9 mW/Gsymbol/s/lane and 0.097 mm2, respectively. The proposed ALDE improves the peak-to-peak time jitter of 12 ps and 34 ps, respectively, for the received data and the recovered clock at a symbol rate of 3 Gsymbol/s/lane. Additionally, the duty cycle ratio of the recovered clock is improved from 42.8% to 48.3%.

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