scholarly journals Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2545
Author(s):  
Kihyun Kim ◽  
Sein Oh ◽  
Hyungil Chae
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Cmos Process ◽  
Noise Shaping ◽  
Mismatch Error ◽  
Analog To Digital ◽  
Current Sharing ◽  
High Sampling Rate ◽  
Good Energy ◽  
Two Phases

A 2-then-1-bit/cycle noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) for high sampling rate and high resolution is presented. The conversion consists of two phases of a coarse 2-bit/cycle SAR conversion for high speed and a fine 1-bit/cycle noise-shaping SAR conversion for high accuracy. The coarse conversion is performed by both voltage and time comparison for low power consumption. A redundancy after the coarse conversion corrects the error caused by a jitter noise during the time comparison. Additionally, a mismatch error between signal and reference paths is eliminated with the help of a tail-current-sharing comparator. The proposed ADC was designed in a 28 nm CMOS process, and the simulation result shows a 68.2 dB signal-to-noise distortion (SNDR) for a sampling rate of 480 MS/s and a bandwidth of 60 MHz with good energy efficiency.

A High Speed Open-Loop Track/Hold Circuit in CMOS Process

2013 ◽  
Vol 756-759 ◽  
pp. 4302-4305
Author(s):  
Zheng Ping Zhang ◽  
Yong Lu Wang ◽  
Ming Liu
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Sampling Rate ◽  
Open Loop ◽  
Cmos Process ◽  
High Sampling ◽  
High Sampling Rate ◽  
Interleaved Structure ◽  
Offset Compensation ◽  
Loop Track

A high speed open-loop track/hold circuit in 0.18um CMOS process is presented. Open-loop and differential architecture are adopted to obtain high bandwidth and high speed;time-interleaved structure is used to reach a high sampling rate;source negative feedback and offset compensation are used to improve the linearity of the circuit.Simulation results show that with 396.875MHz input, 1.6GSPS sampling rate, driving the pre-amplifier of ADC, the thack/hold circuits SFDR(spurious-free dynamic range) is 75.8dB,satisfying the demand of 12 bits ADC.The circuit features high sampling rate,wide bandwidth,high SFDR and universal.

scholarly journals A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology

2021 ◽  
Vol 15 ◽  
pp. 556-568
Author(s):  
Chaya Shetty ◽  
M. Nagabushanam ◽  
Venkatesh Nuthan Prasad
Keyword(s):  
High Speed ◽  
Signal To Noise Ratio ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Sar Adc ◽  
Cmos Process ◽  
Digital To Analog Converter ◽  
Additional Advantage ◽  
Analog To Digital ◽  
Split Capacitor

The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.

scholarly journals A 6-bit Low-Power High-Speed Flash ADC using 180 nm CMOS process

2014 ◽  
Vol 17 (1) ◽  
pp. 52-61
Author(s):  
Thanh Tri Vo ◽  
Trong Tu Bui ◽  
Duc Hung Le ◽  
Cong Kha Pham
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Sampling Rate ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Flash Adc ◽  
High Sampling Rate ◽  
Simulation Results

In this paper we present a design of Flash-ADC that can achieve high performance and low power consumption. By using the Double Sampling Rate technique and a new comparator topology with low kick-back noise, this design can achieve high sampling rate while still consuming low power. The design is implemented in a 0.18 m CMOS process. The simulation results show that this design can work at 400 MSps and power consumption is only 16.24 mW. The DNL and INL are 0.15 LSB and 0.6 LSB, respectively.

scholarly journals A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2260
Author(s):  
Khuram Shehzad ◽  
Deeksha Verma ◽  
Danial Khan ◽  
Qurat Ul Ain ◽  
Muhammad Basim ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Intelligent Transportation System ◽  
Cmos Process ◽  
Process Technology ◽  
Back Issue ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

2014 ◽  
Vol 1049-1050 ◽  
pp. 687-690
Author(s):  
Yu Han Gao ◽  
Ru Zhang Li ◽  
Dong Bing Fu ◽  
Yong Lu Wang ◽  
Zheng Ping Zhang
Keyword(s):  
High Speed ◽  
Binary Code ◽  
Sampling Rate ◽  
Gray Code ◽  
Cmos Technology ◽  
Careful Consideration ◽  
Analog To Digital ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Error Suppression

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

scholarly journals A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 305 ◽  
Author(s):  
Dong Wang ◽  
Xiaoge Zhu ◽  
Xuan Guo ◽  
Jian Luan ◽  
Lei Zhou ◽  
...  
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Power Measurement ◽  
Cmos Process ◽  
Analog To Digital ◽  
Full Speed ◽  
Time Interleaved

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

scholarly journals A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1968
Author(s):  
Juyong Lee ◽  
Seungjun Lee ◽  
Kihyun Kim ◽  
Hyungil Chae
Keyword(s):  
High Resolution ◽  
Power Consumption ◽  
Power Efficiency ◽  
Sampling Rate ◽  
High Gain ◽  
Sar Adc ◽  
Measured Signal ◽  
Noise Shaping ◽  
Analog To Digital ◽  
Digital Correction

In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The (= SNDR + BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.

scholarly journals A Codesigned Integrated Photonic Electronic Neuron

2021 ◽  
Author(s):  
Lorenzo De Marinis ◽  
Alessandro Catania ◽  
Piero Castoldi ◽  
Giampiero Contestabile ◽  
Paolo Bruschi ◽  
...  
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Activation Function ◽  
Memory Storage ◽  
Cmos Process ◽  
Analog To Digital ◽  
Analog Electronics ◽  
Front End ◽  
Execution Speed ◽  
Electronic Neuron

In the modern era of artificial intelligence, increasingly sophisticated artificial neural networks (ANNs) are implemented, which pose challenges in terms of execution speed and power consumption. To tackle this problem, recent research on reduced-precision ANNs opened the possibility to exploit analog hardware for neuromorphic acceleration. In this scenario, photonic-electronic engines are emerging as a short-medium term solution to exploit the high speed and inherent parallelism of optics for linear computations needed in ANN, while resorting to electronic circuitry for signal conditioning and memory storage. In this paper we introduce a precision-scalable integrated photonic-electronic multiply-accumulate neuron, namely PEMAN. The proposed device relies on (i) an analog photonic engine to perform reduced-precision multiplications at high speed and low power, and (ii) an electronic front-end for accumulation and application of the nonlinear activation function by means of a nonlinear encoding in the analog-to-digital converter (ADC). The device, based on the iSiPP50G SOI process for the photonic engine and a commercial 28 nm CMOS process for the electronic front end, has been numerically validated through cosimulations to perform multiply-accumulate operations (MAC). PEMAN exhibits a multiplication accuracy of 6.1 ENOB up to 10 GMAC/s, while it can perform computations up to 56 GMAC/s with a reduced accuracy down to 2.1 ENOB. The device can trade off speed with resolution and power consumption, it outperforms its analog electronics counterparts both in terms of speed and power consumption, and brings substantial improvements also compared to a leading GPU.

scholarly journals Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET

2022 ◽  
Vol 17 ◽  
pp. 1-15
Author(s):  
G. Vasudeva ◽  
B. V. Uma
Keyword(s):  
Low Power ◽  
High Speed ◽  
Performance Metrics ◽  
Sampling Rate ◽  
Geometrical Parameters ◽  
Design Strategies ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Transconductance Amplifier ◽  
And Performance

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logic is designed and integrated to form the ADC architecture with maximum sampling rate of 1 GS/s. Circuit schematic is captured in Cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC is evaluated in MATLAB environment. Differential Non Linearity and Integral Non Linearity metrics for the 12-bit ADC is limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency upto 1 GSps is designed in this work with low power dissipation less than 10 mW.

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