High-Performance Multi-Stage CMOS OTA Design Using Differential Block As Compensation Network

This work presents an effective and straightforward frequency compensation scheme in CMOS three-stage amplifiers. Using a differential block in the compensation network, the proposed circuit shows independent and large first dominant pole regarding the DC gain path. The presented three-stage architecture is frequency-compensated just by a single Miller capacitor. Mathematical analysis is presented along with ample simulations that are performed using TSMC 0.18-[Formula: see text]m CMOS technology. According to the results, the proposed circuit shows DC gain equal to 118[Formula: see text]dB, GBW equal to 466[Formula: see text]MHz, PM equal to 74.3∘ and 1.2[Formula: see text]mW as power consumption, respectively. The high values of DC gain and GBW make the proposed amplifier appropriate for more speedy operations such as high-speed modulators and data converters.

Ventricular fibrillation detection algorithm for automated external defibrillators

The automatic external defibrillator (AED) is a lifesaving device, which processes and analyzes the electrocardiogram (ECG) and prompts a defibrillation shock if ventricular fibrillation is determined. This project investigates the possibility of developing a Ventricular Fibrillation (VF) detection algorithm based on Autoregressive Modeling (AR Modeling) and dominant poles for the use in AEDs. In particular, the ECG segment is modeled using AR modeling and the dominant poles are extracted from the model transfer function. The dominant pole frequencies were then used in classification based on the distance measure. The potential use of this method to distinguish between VF and Normal sinus rhythm (NSR) is discussed. The method was tested with ECG records from the widely recognized databases of American Heart Association (AHA) and the Creighton University (CU). Sensitivity and specificity for the new VF detection method were calculated to be 66% and 94% respectively. The proposed method has some advantages over other existing VF detection algorithms; it has a high detection accuracy, it is computationally inexpensive and can be easily implemented in hardware.

Ventricular fibrillation detection algorithm for automated external defibrillators

The automatic external defibrillator (AED) is a lifesaving device, which processes and analyzes the electrocardiogram (ECG) and prompts a defibrillation shock if ventricular fibrillation is determined. This project investigates the possibility of developing a Ventricular Fibrillation (VF) detection algorithm based on Autoregressive Modeling (AR Modeling) and dominant poles for the use in AEDs. In particular, the ECG segment is modeled using AR modeling and the dominant poles are extracted from the model transfer function. The dominant pole frequencies were then used in classification based on the distance measure. The potential use of this method to distinguish between VF and Normal sinus rhythm (NSR) is discussed. The method was tested with ECG records from the widely recognized databases of American Heart Association (AHA) and the Creighton University (CU). Sensitivity and specificity for the new VF detection method were calculated to be 66% and 94% respectively. The proposed method has some advantages over other existing VF detection algorithms; it has a high detection accuracy, it is computationally inexpensive and can be easily implemented in hardware.

A Dual Frequency Compensation Technique to Improve Stability and Transient Response for a Three Stage Low-Drop-Out Linear Regulator

A novel internal compensation technique named dual frequency compensation is proposed to improve the stability and the transient response of the on-chip output capacitor three stage low-drop-out linear voltage regulator (LDO). It exploits a combination of amplification and differentiation to sufficiently separate the dominant pole from the first non-dominant pole so that the latter is located after the unity gain frequency regardless of the load current value. The proposed LDO regulator is analyzed, designed, and simulated in standard 0.18 µm low voltage CMOS technology. The presented LDO regulator delivers a stable voltage of 1.2 V for an input supply voltage range of 1.35-1.85 V with a maximum line deviation of 4.68mV/V and can supply up to 150mA of the load current. The maximum transient variation of the output voltage is 54.5 mV when the load current pulses from 150mA to 0mA during a fall time of 1µs. The proposed LDO regulator has a low figure of merit compared with recent LDO regulators.

Análise da Evolução dos Modos Interárea do SIN no Hozironte de 2020 a 2024

Este trabalho avalia a evolução dos principais modos interárea do SIN no horizonte de 2020 - 2024, considerando cenários de elevada geração eólica e solar fotovoltaica no Nordeste. O programa computacional PacDyn é adotado nas simulações com o algoritmo Dominant Pole Spectrum Eigensolver (DPSE) para a identificação dos modos de interesse. Além disto, são estudados os impactos de obras de ampliação das Interligações do SIN sobre os modos interárea.

Gain-Based Double Feedforward Compensation for Multi-Stage Amplifiers

A gain-based double feedforward compensation (GBDFC) for multi-stage amplifiers is proposed, which could be used in multi-stage OTA design. The proposed compensation technique provides two left-plane zeros to counteract with the first and second non-dominant poles of the OTA without reducing the dominant pole obviously. Meanwhile, a high slew-rate is presented in the condition of large step input signal. A three-stage Opamp prototype with the proposed technique is realized in a 0.18 yitm CMOS process. The post simulation results show that it provides a unity-gain bandwidth (GBW) of 103 MHz and phase margin (PM) of 70° with power consumption of 0.328 mW and small compensation capacitors, implying a better FOM compare with the state-of-the-art.