Gain-Based Double Feedforward Compensation for Multi-Stage Amplifiers

2021 ◽  
Vol 16 (2) ◽  
pp. 196-200
Author(s):  
Feng Xiaojia ◽  
Zhang Jun-An
Keyword(s):  
State Of The Art ◽  
Cmos Process ◽  
Phase Margin ◽  
Gain Bandwidth ◽  
Dominant Pole ◽  
Multi Stage ◽  
Large Step ◽  
Unity Gain ◽  
Compensation Technique ◽  
Simulation Results

A gain-based double feedforward compensation (GBDFC) for multi-stage amplifiers is proposed, which could be used in multi-stage OTA design. The proposed compensation technique provides two left-plane zeros to counteract with the first and second non-dominant poles of the OTA without reducing the dominant pole obviously. Meanwhile, a high slew-rate is presented in the condition of large step input signal. A three-stage Opamp prototype with the proposed technique is realized in a 0.18 yitm CMOS process. The post simulation results show that it provides a unity-gain bandwidth (GBW) of 103 MHz and phase margin (PM) of 70° with power consumption of 0.328 mW and small compensation capacitors, implying a better FOM compare with the state-of-the-art.

A LOW POWER CURRENT RECYCLING CONSTANT-gm RAIL-TO-RAIL OTA

2014 ◽  
Vol 23 (02) ◽  
pp. 1450022
Author(s):  
XIAO ZHAO ◽  
HUAJUN FANG ◽  
JUN XU
Keyword(s):  
Low Power ◽  
Bias Current ◽  
Cmos Process ◽  
Slew Rate ◽  
Gain Bandwidth ◽  
Design Specifications ◽  
Rail To Rail ◽  
Dc Gain ◽  
Unity Gain ◽  
Simulation Results

A low power current recycling constant-gm rail-to-rail (RtR) OTA is presented. The proposed amplifier has the benefit of delivering the same performance while consuming half the power compared to the conventional RtR amplifier. This is achieved by recycling the bias current of idle devices, which results in an enhanced transconductance, gain and slew rate. The proposed amplifier was implemented in CSMC standard 0.18 um CMOS process. Simulation results show that the proposed amplifier achieves 10.2 MHz unity-gain bandwidth, 59.4 dB DC gain, 4.8 V/us slew rate and less than 8% deviation in transconductance, but the power consumption reduced by 50% compared to the conventional RtR amplifier with the same design specifications.

Design of High Gain CMOS Folded Cascode Operational Amplifier

2013 ◽  
Vol 389 ◽  
pp. 573-578
Author(s):  
Ming Xin Song ◽  
Yue Li ◽  
Meng Meng Xu
Keyword(s):  
Power Supply ◽  
Operational Amplifier ◽  
High Gain ◽  
Cmos Process ◽  
Phase Margin ◽  
Gain Bandwidth ◽  
Input Stage ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

A high-gain folded cascode operational amplifier is presented. Structure of folded cascode operational amplifier and manual calculations are discussed in detail. Folded cascode structure for the input stage is adopted. Folded cascode structure can increase the gain and the value of PSRR. Folded cascode structure can also allow self-compensation at the output. The operational amplifier is designed in 0.35μm CMOS process with 5V power supply. The operational amplifier has high-gain and work steadily. The results of SPICE simulations are shown that the operational amplifier achieved dc gain of 110dB with unity-gain bandwidth of 74.3MHz and phase margin of 54.4 degree.

ACTIVE-FEEDBACK SINGLE MILLER CAPACITOR FREQUENCY COMPENSATION TECHNIQUES FOR THREE-STAGE AMPLIFIERS

2010 ◽  
Vol 19 (07) ◽  
pp. 1381-1398 ◽  
Author(s):  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Small Signal ◽  
Frequency Compensation ◽  
Gain Bandwidth ◽  
Silicon Area ◽  
Active Feedback ◽  
In Series ◽  
Unity Gain ◽  
Simulation Results ◽  
A Current

This paper presents two novel active-feedback single Miller capacitor frequency compensation techniques for low-power three-stage amplifiers. These techniques include the active-feedback single Miller capacitor frequency compensation (AFSMC) and the dual active-feedback single Miller capacitor frequency compensation (DAFSMC). In the proposed techniques, only one Miller capacitor in series with a current buffer is utilized. The main advantages of the proposed three-stage amplifiers are the enhanced unity-gain bandwidth and the reduced silicon area. Small-signal analyses are performed and the design equations are obtained. Extensive HSPICE simulation results are provided to show the usefulness of the proposed AFSMC and DAFSMC amplifiers in both large and small capacitive loads.

The Design of the Integrator of Sigma-Delta Modulator

2013 ◽  
Vol 562-565 ◽  
pp. 477-481
Author(s):  
Xiao Wei Liu ◽  
Song Chen ◽  
Liang Liu ◽  
Jian Yang ◽  
Wei Ping Chen
Keyword(s):  
Low Frequency ◽  
Clock Signal ◽  
Gain Bandwidth ◽  
Two Phase ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Fully Differential ◽  
Unity Gain ◽  
Simulation Results ◽  
Sigma Delta Adc

A kind of fully differential integrator is designed for the modulator of Sigma-delta ADC in this paper. Fully differential structure is adopted to enlarge the amplitude of output, restrain nonlinearity and increase competence of anti-interference. The frequency of signal in this design is 10kHz and the frequency of clock signal is 100kHz. The design of fully differential integrator, capacitive common mode feedback, two-phase unoverlapping clock and switched capacitor integrator are accomplished in this paper. The simulation results in Cadence using 0.5um process show that the low-frequency gain of operational amplifier is 69.87dB, unity gain bandwidth is 37.74MHz, phase margin is 67.73 degrees and slew rate is more than 31V/μs.

scholarly journals Improved Frequency Compensation Technique for Three-Stage Amplifiers

2021 ◽  
Vol 11 (1) ◽  
pp. 11
Author(s):  
Alejandro Roman Loera ◽  
Anurag Veerabathini ◽  
Luis Alejandro Flores Oropeza ◽  
Luis Antonio Carrillo Martínez ◽  
David Moro Frias
Keyword(s):  
Detailed Comparison ◽  
Cmos Process ◽  
Slew Rate ◽  
Compensation Scheme ◽  
Frequency Compensation ◽  
Output Node ◽  
Miller Compensation ◽  
Compensation Technique ◽  
Simulation Results ◽  
Nested Miller Compensation

Improved frequency compensation is proposed for a three-stage amplifier with reduced total capacitance, improved slew rate, and reduced settling time. The proposed compensation uses an auxiliary feedback to increase the total effective compensation capacitance without loading the output node. The proposed compensation scheme is validated in simulation by implementing a three-stage amplifier driving 10 pF load capacitor in a 0.18 μm CMOS process. A detailed comparison of the compensation with a conventional nested Miller compensation is also presented. The simulation results showed a reduction in total compensation capacitance and improvement in slew rate compared to conventional nested Miller compensation and the other reported techniques in the literature.

A CMOS Bandgap Reference with Temperature Compensation

2014 ◽  
Vol 667 ◽  
pp. 401-404
Author(s):  
Xi Chen ◽  
Liang Li ◽  
Xing Fa Huang ◽  
Xiao Feng Shen ◽  
Ming Yuan Xu
Keyword(s):  
Temperature Compensation ◽  
High Order ◽  
Cmos Process ◽  
Threshold Region ◽  
Bandgap Reference ◽  
Mos Transistor ◽  
First Order ◽  
Reference Circuit ◽  
Compensation Technique ◽  
Simulation Results

This paper has presented a bandgap reference circuit with high-order temperature compensation. The compensation technique is achieved by using MOS transistor operating in sub-threshold region for reducing high-order TC of Vbe. The circuit is designed in 0.18¦Ìm CMOS process. Simulation results show that the proposed circuit achieves 4.2 ppm/¡æ with temperature from-55 to 125 ¡æ, which is only a third than that of first-order compensated bandgap reference.

A Sub-1V High Precision CMOS Bandgap Reference

2013 ◽  
Vol 427-429 ◽  
pp. 1097-1100
Author(s):  
Qian Neng Zhou ◽  
Rong Xue ◽  
Hong Juan Li ◽  
Jin Zhao Lin ◽  
Yun Song Li ◽  
...  
Keyword(s):  
Temperature Coefficient ◽  
Power Supply ◽  
Output Voltage ◽  
Supply Voltage ◽  
Piecewise Linear ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Power Supply Voltage ◽  
Compensation Technique ◽  
Simulation Results

In this paper, a low temperature coefficient bandgap voltage (BGR) is designed for A/D converter by adopting piecewise-linear compensation technique. The designed BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the PSRR of the designed BGR achieves-72.51dB, -72.49dB, and-70.58dB at 10Hz, 100Hz and 1kHz respectively. The designed BGR achieve the temperature coefficient of 1.57 ppm/°C when temperature is in the range from-35°C to 125°C. When power supply voltage VDD changes from 1V to 7V, the deviation of the designed BGR output voltage VREF is only 4.465μV.

Multistage Amplifier Using Dual-Miller with Nulling-Resistor and Dual-Feedforward Structure

2014 ◽  
Vol 989-994 ◽  
pp. 1169-1172
Author(s):  
Qian Neng Zhou ◽  
Qi Li ◽  
Jin Zhao Lin ◽  
Hong Juan Li ◽  
Chen Li ◽  
...  
Keyword(s):  
High Gain ◽  
Phase Margin ◽  
Slew Rate ◽  
Well Performance ◽  
Gain Bandwidth ◽  
Wide Bandwidth ◽  
Miller Compensation ◽  
Dc Gain ◽  
Simulation Results ◽  
Multistage Amplifier

This paper designs a high-gain wide-bandwidth multistage amplifier by employing the dual-miller compensation with nulling-resistor and dual-feedforward compensation (DMCNR-DFC) in 0.35μm BCD process. The designed DMCNR-DFC multistage amplifier achieves well performance including gain-bandwidth product (GBW) and slew rate (SR). Simulation results show that the DMCNR-DFC multistage amplifier achieves a dc gain of about 121.1dB and GBW of about 6.1MHz with 52o phase margin.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

LOW POWER CONTINUOUS TIME COMMON MODE SENSING FOR COMMON MODE FEEDBACK CIRCUITS

2010 ◽  
Vol 19 (03) ◽  
pp. 519-528 ◽  
Author(s):  
M. PRAMOD ◽  
T. LAXMINIDHI
Keyword(s):  
Continuous Time ◽  
Input Impedance ◽  
Cmos Process ◽  
High Input ◽  
High Input Impedance ◽  
Common Mode ◽  
Standby Power ◽  
Low Distortion ◽  
Simulation Results ◽  
Feedback Circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 μm CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27–34% less power than previous high swing CMFB circuits.

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