High-Performance Multi-Stage CMOS OTA Design Using Differential Block As Compensation Network

2021 ◽  
Author(s):  
Behnam Babazadeh Daryan ◽  
Hassan Khalesi ◽  
Vahid Ghods
Keyword(s):  
Mathematical Analysis ◽  
High Speed ◽  
High Performance ◽  
Cmos Technology ◽  
Data Converters ◽  
Compensation Scheme ◽  
Frequency Compensation ◽  
Dominant Pole ◽  
Multi Stage ◽  
Dc Gain

This work presents an effective and straightforward frequency compensation scheme in CMOS three-stage amplifiers. Using a differential block in the compensation network, the proposed circuit shows independent and large first dominant pole regarding the DC gain path. The presented three-stage architecture is frequency-compensated just by a single Miller capacitor. Mathematical analysis is presented along with ample simulations that are performed using TSMC 0.18-[Formula: see text]m CMOS technology. According to the results, the proposed circuit shows DC gain equal to 118[Formula: see text]dB, GBW equal to 466[Formula: see text]MHz, PM equal to 74.3∘ and 1.2[Formula: see text]mW as power consumption, respectively. The high values of DC gain and GBW make the proposed amplifier appropriate for more speedy operations such as high-speed modulators and data converters.

scholarly journals High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

2021 ◽  
pp. 263-269
Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa
Keyword(s):  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Power Performance ◽  
High Speed Design ◽  
Power Delay Product ◽  
Full Swing ◽  
Output Swing ◽  
High Output

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

A Low-Cost Highly Reliable Spintronic True Random Number Generator Circuit for Secure Cryptography

SPIN ◽  
2019 ◽  
Vol 10 (01) ◽  
pp. 2050003 ◽  
Author(s):  
Iman Alibeigi ◽  
Abdolah Amirany ◽  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Saeed Bagheri Shouraki
Keyword(s):  
High Speed ◽  
High Performance ◽  
Random Number ◽  
Low Cost ◽  
Random Number Generator ◽  
Magnetic Tunnel Junction ◽  
Random Number Generation ◽  
Cmos Technology ◽  
Random Numbers ◽  
Number Generation

Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in special states. Generated random bit at the output of the proposed circuit is returned to the write circuit to be written in the relevant cell for the next random generation. In a random bitstream, all bits must have the same chance of being “0”or “1”. We have proposed a new XOR-based method in this paper to resolve this issue in multiple random generators that produce truly random numbers with a different number of ones and zeros in the output stream. The simulation results using a 45[Formula: see text]nm CMOS technology with a special model of MTJ validated the advantages offered by the proposed circuit.

Integrated Optoelectronic Devices on Silicon

2012 ◽  
Vol 1396 ◽  
Author(s):  
Di Liang ◽  
John E. Bowers
Keyword(s):  
Output Power ◽  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Continuous Wave ◽  
Light Emission ◽  
Extinction Ratio ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Pockels Effect

ABSTRACTSilicon (Si) has been the dominating material platform of microelectronics over half century. Continuous technological advances in circuit design and manufacturing enable complementary metal-oxide semiconductor (CMOS) chips with increasingly high integration complexity to be fabricated in an unprecedently scale and economical manner. Conventional Si-based planar lightwave circuits (PLCs) has benefited from advanced CMOS technology but only demonstrate passive functionalities in most circumstances due to poor light emission efficiency and weak major electro-optic effects (e.g., Pockels effect, the Kerr effect and the Franz–Keldysh effect) in Si. Recently, a new hybrid III-V-on-Si integration platform has been developed, aiming to bridge the gap between Si and III-V direct-bandgap materials for active Si photonic integrated circuit applications. Since then high-performance lasers, amplifiers, photodetectors and modulators, etc. have been demonstrated. Here we review the most recent progress on hybrid Si lasers and high-speed hybrid Si modulators. The former include distributed feedback (DFB) lasers showing over 10 mW output power and up to 85 oC continuous-wave (cw) operation, compact hybrid microring lasers with cw threshold less than 4 mA and over 3 mW output power, and 4-channel hybrid Si AWG lasers with channel space of 360 GHz. Recently fabricated traveling-wave electro-absorption modulators (EAMs) and Mach-Zehnder interferometer modulators (MZM) on this platform support 50 Gb/s and 40 Gb/s data transmission with over 10 dB extinction ratio, respectively.

scholarly journals Design of interfaces between high speed data converters and high performance FPGAs for software defined radio applications

2019 ◽  
Vol 71 (4) ◽  
pp. 601-614 ◽  
Author(s):  
Mahadevan Balakrishnan ◽  
Khalim Amjad Meerja ◽  
Kishore Kumar Gundugonti ◽  
Sri Rama Krishna Kalva
Keyword(s):  
Software Defined Radio ◽  
High Speed ◽  
High Performance ◽  
Data Converters ◽  
High Speed Data

scholarly journals Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-5 ◽  
Author(s):  
Shikha Panwar ◽  
Mayuresh Piske ◽  
Aatreya Vivek Madgula
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Room Temperature ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Cmos Circuits ◽  
Output Node ◽  
Critical Sections

This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

scholarly journals Buried Powered 4t Sram with Improved Write Margin

2020 ◽  
Vol 9 (3) ◽  
pp. 2348-2351
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Cmos Technology ◽  
Sram Cell

The main intention of this paper is to understand clearly about the high performance of 4T-SRAM with an improved write margin. the power consumption is often reduced considerably by using a buried power rail (BPR) to the SRAM cell, which reduces the resistance of bit line and word line. The write margin is often increased by the fine standardization of metal dimensions within the SRAM cell. Conventionally, 4T-SRAM cell offers high speed and fewer space compared to 6T-SRAM cell. 4T-SRAM is actualized using 130nm CMOS Technology.

A Compact High-Performance 10-bit 30-Channel OLED Driver Using Switched Capacitor Circuit for High-Linearity Application

2021 ◽  
pp. 2250013
Author(s):  
Neeru Agarwal ◽  
Neeraj Agarwal ◽  
Chih-Wen Lu
Keyword(s):  
Power Consumption ◽  
Output Voltage ◽  
High Speed ◽  
High Performance ◽  
Input Voltage ◽  
Cmos Technology ◽  
Settling Time ◽  
Switched Capacitor ◽  
Voltage Range ◽  
High Output Voltage

This work proposes a new OLED driver architecture with 10-bit segmented DAC and switched capacitor multiply-by-two circuit application. A 30-channel 10-bit switched capacitor driver chip prototype is implemented in 0.18-[Formula: see text]m CMOS technology. In this architecture, the achieved output range is 1.5–4.8[Formula: see text]V for an input range of 1.5–3.15[Formula: see text]V, which is suitable for OLED driver with different colors. This architecture is not only converting the digital input signal to analog output for the display panel but also giving amplified high output voltage range. In the segmented DAC, 6-bit coarse DAC and 4-bit fine DAC are used for the input voltage range 1.5–3.15[Formula: see text]V. In a conventional RDAC for the output voltage of 4.8[Formula: see text]V, it requires 2[Formula: see text] switches i.e., 14-bit RDAC for the same resolution. Hence, conventional RDAC driver is four times larger than the proposed innovative very compact and high speed 10-bit segmented DAC switched capacitor OLED driver. The new architecture drastically reduces the number of switches and complex metal routing which results in reduced power consumption and good settling time. In the proposed OLED driver, no extra buffer is required as switched capacitor op-amp is applied for the same purpose with a gain of more than one. This high-resolution design with small die area also improves the linearity and uniformity with low-power consumption. The post-simulated results show that the OLED driver exhibits the maximum DNL and INL of 0.03 LSB and [Formula: see text]0.06 LSB, respectively, with an LSB voltage of 3[Formula: see text]mV. The one-channel area is 0.586[Formula: see text]mm [Formula: see text] 0.017[Formula: see text]mm and the settling time is 4.25[Formula: see text][Formula: see text]s for 30[Formula: see text]k[Formula: see text] and 30[Formula: see text]pF driving load.

A High-Performance Sigma-Delta Modulator in 0.18μm CMOS Technology

2014 ◽  
Vol 519-520 ◽  
pp. 1085-1088
Author(s):  
Ying Qi Qian ◽  
Chang Chun Zhang ◽  
Zhong Chao Liu ◽  
Lei Lei Liu ◽  
Yu Rong Luan ◽  
...  
Keyword(s):  
Radio Frequency Identification ◽  
High Speed ◽  
High Performance ◽  
Dynamic Range ◽  
Low Voltage ◽  
Intermediate Frequency ◽  
Cmos Technology ◽  
High Gain ◽  
Sigma Delta Modulator ◽  
Sigma Delta

Sigma-Delta (∑∆) modulators are commonly used in high-resolution analog-to-digital converters (ADCs). In this paper, a high-performance modulator targeted for ultra-high-frequency (UHF) radio-frequency identification (RFID) zero-intermediate frequency (ZIF) receivers is designed in standard 0.18μm CMOS technology. The modulator has been designed with switched-capacitor (SC) integrators employing gain-boosted operational amplifiers, voltage comparators and nonoverlapping clock generators to satisfy such requirements as high gain, low voltage and wide bandwidth. The behavioral-level modeling and circuit-level design are carried out with MATLAB/Simulink and Cadence/SpectreRF, respectively. Ultimately, the high-speed and low-power realization of a second-order single-bit modulator with an oversampling ratio (OSR) of 32 is presented. Simulation results shown that, from a 1.8V supply, operated at a sampling frequency of 64MHz, a dynamic range of 53.4dB over a signal bandwidth of 1MHz is achieved.

Numerical Investigation of VSVs Mal-Schedule Effects in a Three-Stage Axial Compressor

2014 ◽  
Author(s):  
Yan-Ling Li ◽  
Abdulnaser Sayma
Keyword(s):  
High Speed ◽  
High Performance ◽  
Numerical Study ◽  
Axial Compressor ◽  
Rotating Stall ◽  
Multi Stage ◽  
Flow Features ◽  
Grid Points ◽  
Stage Matching ◽  
Outflow Boundary

Variable Stator Vanes (VSVs) are commonly used in multi-stage axial compressors for stage matching at part load operations and during start up. Improper VSVs settings or malfunction of the controlling actuator system can lead to compressor instabilities including rotating stall and surge. It is important to be able to predict the aerodynamic behaviour of compressors in such events to either produce tolerant designs or incorporate diagnosis and recovery systems. This paper presents a numerical study of a compressor operating near the stall boundary for a mal-scheduled VSVs case. A high-speed three-stage axial compressor with Inlet Guide Vanes (IGV) is used in the investigation because of its relative simplicity and availability of geometry and aerodynamic data. A 3D RANS viscous unsteady time-accurate flow solver was used to perform the full annulus simulation with a downstream variable nozzle to control outflow boundary conditions. The unstructured mesh contained about 25 million grid points and the simulation was performed on a high performance computing cluster for many engine rotations. Rotating stall with one single cell covering several passages in all three rotors was predicted which propagated at approximately half of the shaft speed. Full analysis of the flow features is presented in the paper.

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