scholarly journals A Dual Frequency Compensation Technique to Improve Stability and Transient Response for a Three Stage Low-Drop-Out Linear Regulator

2021 ◽  
Vol 8 (2) ◽  
pp. 219-229
Author(s):  
Anass Slamti ◽  
Youness Mehdaoui ◽  
Driss Chenouni ◽  
Zakia Lakhliai
Keyword(s):  
Transient Response ◽  
Low Voltage ◽  
Drop Out ◽  
Frequency Compensation ◽  
Dual Frequency ◽  
Load Current ◽  
Voltage Range ◽  
Dominant Pole ◽  
Compensation Technique ◽  
Ldo Regulator

A novel internal compensation technique named dual frequency compensation is proposed to improve the stability and the transient response of the on-chip output capacitor three stage low-drop-out linear voltage regulator (LDO). It exploits a combination of amplification and differentiation to sufficiently separate the dominant pole from the first non-dominant pole so that the latter is located after the unity gain frequency regardless of the load current value. The proposed LDO regulator is analyzed, designed, and simulated in standard 0.18 µm low voltage CMOS technology. The presented LDO regulator delivers a stable voltage of 1.2 V for an input supply voltage range of 1.35-1.85 V with a maximum line deviation of 4.68mV/V and can supply up to 150mA of the load current. The maximum transient variation of the output voltage is 54.5 mV when the load current pulses from 150mA to 0mA during a fall time of 1µs. The proposed LDO regulator has a low figure of merit compared with recent LDO regulators.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

Frequency-Compensated Bulk-Driven TIA Suitable for Low-Voltage Low-Power Applications

2020 ◽  
pp. 2150121
Author(s):  
Urvashi Bansal ◽  
Maneesha Gupta ◽  
Niranjan Raj
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Transimpedance Amplifier ◽  
Frequency Compensation ◽  
Suitable Alternative ◽  
Small Signal Analysis ◽  
Cmos Design ◽  
Spiral Inductors ◽  
Compensation Technique ◽  
Good Agreement

The importance of a transimpedance amplifier in an optical transceiver is very well known. In this paper, a novel CMOS design of the bulk-driven transimpedance amplifier (BD-TIA) is given where the bridge-shunt peaking-based frequency compensation technique is exploited to improve frequency response. A pre-existing active inductor has been used for the same. The electrical characteristics and functioning of this inductor simulator make it a suitable alternative to both floating and grounded spiral inductors. In order to verify the workability of the proposed circuit, it has been simulated with TSMC CMOS 0.18[Formula: see text][Formula: see text]m process parameters. The proposed circuit is useful in low-voltage low-power VLSI applications as it uses a single supply of 0.75[Formula: see text]V. The power consumption of BD-TIA is very low, being 0.37[Formula: see text]mW, because a standard MOSFET has been replaced by a bulk-driven MOSFET (BDMOS), while the 3-dB bandwidth is observed to be 4.5[Formula: see text]GHz. The mathematical investigation and small signal analysis show that the simulation results are in good agreement.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

A LDO REGULATOR WITH PRE-REGULATOR AND MULTI-ZERO AND MULTI-POLE FREQUENCY COMPENSATION

2013 ◽  
Vol 22 (10) ◽  
pp. 1340028 ◽  
Author(s):  
YONGSHENG WANG ◽  
XIAOXIONG FENG ◽  
BEI CAO
Keyword(s):  
Power Supply ◽  
High Frequency ◽  
Low Frequency ◽  
Frequency Compensation ◽  
Battery System ◽  
Linear Regulator ◽  
Dominant Pole ◽  
Output Capacitor ◽  
Ldo Regulator ◽  
Load Conditions

A low dropout (LDO) linear regulator with pre-regulator is presented in this paper. The LDO is suitable for wide power supply of 4.5–28 V for smart battery system applications to generate a stable 1.8 V output. The proposed LDO provides high stability by pre-regulator for a rough 3.3 V as internal power supply and multi-zero and multi-pole frequency compensation. The scheme of combining of using output capacitor to set a dominant pole, utilizing a buffer stage to avoid generation of low-frequency pole, introducing an additional zero, is presented to stabilize the regulator loop for various load conditions and wide supply range. Besides, parasitic poles in high frequency can be compensated by feed-forward compensation and mirror-pole compensation.

scholarly journals A 0.18-ns Response Time Digital LDO Regulator with Adaptive PI Controller in 180-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1668
Author(s):  
Shengping Lv ◽  
Peiyuan Wan ◽  
Hongda Zhang ◽  
Jiarong Geng ◽  
Jiabao Wen ◽  
...  
Keyword(s):  
Response Time ◽  
Transient Response ◽  
Output Voltage ◽  
Clock Cycle ◽  
Response Speed ◽  
Drop Out ◽  
Cmos Process ◽  
Error Detector ◽  
Current Steps ◽  
Ldo Regulator

Digital low drop-out regulator (D-LDO) with fast settling time and superior transient response is gaining increasing attention to make up for the deficiency of analog LDO. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. In this paper, a multi-bit conversion technique is proposed to improve the transient response speed. The multi-bit conversion technique is achieved by an error detector with adaptive regulation of proportion and integration parameters in the digital controller before pass devices. Besides, a voltage sensor and a time-to-digital converter are employed to convert the output voltage to digital codes. Implemented in a 180-nm CMOS process, the proposed D-LDO features under 36/33 mV of undershoot/overshoot at VOUT = 0.95 V as the load current steps up with 40 mA/1 ns on a 0.5 nF load capacitor. The simulated response time is 0.18-ns, the figure-of-merit of speed FOM1 is 0.65 ps and FOM2 achieves 0.068 pF.

A 2 × VDD-Enabled Output-Capacitor-Free Low-Dropout Regulator with Fast Transient Response for Low-Cost System-on-Chip

2018 ◽  
Vol 27 (09) ◽  
pp. 1850143
Author(s):  
Shuangxing Zhao ◽  
Chenchang Zhan ◽  
Guigang Cai
Keyword(s):  
Transient Response ◽  
Low Voltage ◽  
System On Chip ◽  
Cmos Process ◽  
Fast Transient Response ◽  
Power Transistors ◽  
Fast Transient ◽  
On Chip ◽  
Output Capacitor ◽  
Ldo Regulator

This paper presents a [Formula: see text]-enabled output-capacitor-free CMOS low-dropout (LDO) regulator with fast transient response for cost-effective system-on-chip (SoC) power management applications with elevated-[Formula: see text] supply. All the MOS transistors used in the proposed LDO regulator are low voltage (LV) MOSFETs, hence saving the high voltage devices fabrication cost required in a conventional design. Two LV power transistors are cascaded in the power train. A mid-rail regulator is used to generate [Formula: see text] voltage for the power transistors as well as the main error amplifier to guarantee safe operation. The mid-rail regulator employs stacking transistors to handle the high supply voltage. Moreover, Miller compensation with adaptive biasing is used to achieve good stability and fast transient response. A proof-of-concept design is fabricated in a standard 0.18-[Formula: see text]m CMOS process which achieves 3.3–3.6[Formula: see text]V nominal input, 3.1[Formula: see text]V nominal output and 100[Formula: see text]mA loading capability with all the transistors being 1.8[Formula: see text]V MOSFETs.

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