Effects of Bonding Process Parameters on Wafer-to-Wafer Alignment Accuracy in Benzocyclobutene (BCB) Dielectric Wafer Bonding

2005 ◽  
Vol 863 ◽  
Author(s):  
F. Niklaus ◽  
R.J. Kumar ◽  
J.J. McMahon ◽  
J. Yu ◽  
T. Matthias ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Layer Thickness ◽  
Wafer Bonding ◽  
Three Dimensional ◽  
Bonding Process ◽  
Alignment Accuracy ◽  
Wafer Level ◽  
Bonding Parameters ◽  
Wafer Pair ◽  
The Impact

AbstractWafer-level three-dimensional (3D) integration is an emerging technology to increase the performance and functionality of integrated circuits (ICs). Aligned wafer-to-wafer bonding with dielectric polymer layers (e.g., benzocyclobutene (BCB)) is a promising approach for manufacturing of 3D ICs, with minimum bonding impact on the wafer-to-wafer alignment accuracy essential. In this paper we investigate the effects of thermal and mechanical bonding parameters on the achievable post-bonding wafer-to-wafer alignment accuracy for polymer wafer bonding with 200 mm diameter wafers. Our baseline wafer bonding process with softbaked BCB (∼35% cross-linked) has been modified to use partially cured (∼ 43% crosslinked) BCB. The partially cured BCB layer does not reflow during bonding, minimizing the impact of inhomogeneities in BCB reflow under compression and/or slight shear forces at the bonding interface. As a result, the non-uniformity of the BCB layer thickness after wafer bonding is less than 0.5% of the nominal layer thickness and the wafer shift relative to each other during the wafer bonding process is less than 1 μm (average) for 200 mm diameter wafers. The critical adhesion energy of a bonded wafer pair with the partially cured BCB wafer bonding process is similar to that with soft-baked BCB.

200. mm Silicon Wafer-to-Wafer Bonding with Thin Ti Layer under BEOL-Compatible Process Conditions

2004 ◽  
Vol 843 ◽  
Author(s):  
J. Yu ◽  
J. J. McMahon ◽  
J.-Q. Lu ◽  
R. J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Complete Removal ◽  
External Pressure ◽  
Reduced Form ◽  
Process Conditions ◽  
Manufacturing Cost ◽  
Wafer Level ◽  
Integrity Test ◽  
Wafer Pair

ABSTRACTWafer level monolithic three-dimensional (3D) integration is an emerging technology to realize enhanced performance and functionality with reduced form-factor and manufacturing cost. The cornerstone for this 3D processing technology is full-wafer bonding under back-end-of-the-line (BEOL) compatible process conditions. For the first time to our knowledge, we demonstrate nearly void-free 200 mm wafer-to-wafer bonding with an ultra-thin Ti adhesive coating, annealed at BEOL-compatible temperature (400 °C) in vacuum with external pressure applied. Mechanical integrity test showed that bonded wafer pair survived after a stringent three-step thinning process (grinding/polishing/wet-etching) with complete removal of top Si wafer, while allowing optical inspection of bonding interface. Mechanisms contributing to the strong bonding at Ti/Si interface are briefly discussed.

scholarly journals Photonic Integration on the Hybrid Silicon Evanescent Device Platform

2008 ◽  
Vol 2008 ◽  
pp. 1-17 ◽  
Author(s):  
Hyundai Park ◽  
Alexander W. Fang ◽  
Di Liang ◽  
Ying-Hao Kuo ◽  
Hsu-Hao Chang ◽  
...  
Keyword(s):  
Low Temperature ◽  
Integrated Circuits ◽  
Wafer Bonding ◽  
Optical Gain ◽  
Hybrid Structure ◽  
Bonding Process ◽  
Wafer Level ◽  
Device Structure ◽  
Silicon Waveguides ◽  
Hybrid Silicon

This paper reviews the recent progress of hybrid silicon evanescent devices. The hybrid silicon evanescent device structure consists of III-V epitaxial layers transferred to silicon waveguides through a low-temperature wafer bonding process to achieve optical gain, absorption, and modulation efficiently on a silicon photonics platform. The low-temperature wafer bonding process enables fusion of two different material systems without degradation of material quality and is scalable to wafer-level bonding. Lasers, amplifiers, photodetectors, and modulators have been demonstrated with this hybrid structure and integration of these individual components for improved optical functionality is also presented. This approach provides a unique way to build photonic active devices on silicon and should allow application of silicon photonic integrated circuits to optical telecommunication and optical interconnects.

Fine Keyed Alignment and Bonding for Wafer-Level 3D ICs

2006 ◽  
Vol 914 ◽  
Author(s):  
Sang Hwui Lee ◽  
Frank Niklaus ◽  
J. Jay McMahon ◽  
Jian Yu ◽  
Ravi J. Kumar ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
State Of The Art ◽  
Three Dimensional ◽  
Alignment Accuracy ◽  
Wafer Level ◽  
Alignment Procedure ◽  
3D Ics ◽  
Side Walls ◽  
The One ◽  
Wafer Surfaces

AbstractPrecise wafer-to-wafer alignment accuracy is crucial to interconnecting circuits on different wafers in three dimensional integrated circuits. We discuss the use of fabricated structures on wafer surfaces to mechanically achieve higher alignment accuracy than can be achieved with our existing (baseline) alignment protocol. The keyed alignment structures rely on structures with tapered side-walls that can slide into each after two wafers are “pre-aligned” using our baseline alignment protocol. Results indicate that alignment accuracy is about a quarter micron, well below the one micron alignment accuracy obtained in our baseline alignment procedure using commercial state-of-the-art wafer alignment equipment. In addition to improving alignment, the alignment structures also hinder undesirable bonding-induced misalignment. The keyed alignment structures are also promising for nano-imprint lithography.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

Stress-strain curve of paper revisited

2012 ◽  
Vol 27 (2) ◽  
pp. 318-328 ◽  
Author(s):  
Svetlana Borodulina ◽  
Artem Kulachenko ◽  
Mikael Nygårds ◽  
Sylvain Galland
Keyword(s):  
Three Dimensional ◽  
Strain Curve ◽  
Failure Behavior ◽  
Three Dimensional Model ◽  
Stress Strain Curve ◽  
Stress Strain ◽  
Fiber Network ◽  
Bonding Parameters ◽  
Particle Level ◽  
The Impact

Abstract We have investigated a relation between micromechanical processes and the stress-strain curve of a dry fiber network during tensile loading. By using a detailed particle-level simulation tool we investigate, among other things, the impact of “non-traditional” bonding parameters, such as compliance of bonding regions, work of separation and the actual number of effective bonds. This is probably the first three-dimensional model which is capable of simulating the fracture process of paper accounting for nonlinearities at the fiber level and bond failures. The failure behavior of the network considered in the study could be changed significantly by relatively small changes in bond strength, as compared to the scatter in bonding data found in the literature. We have identified that compliance of the bonding regions has a significant impact on network strength. By comparing networks with weak and strong bonds, we concluded that large local strains are the precursors of bond failures and not the other way around.

Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000698-000725 ◽  
Author(s):  
Kai Zoschke ◽  
Klaus-Dieter Lang
Keyword(s):  
Wafer Bonding ◽  
Rf Mems ◽  
Electrical Contacts ◽  
Bonding Process ◽  
Frame Structure ◽  
Back Side ◽  
Wafer Level ◽  
Free Standing ◽  
Carrier Wafer ◽  
Base Substrate

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.

Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-24
Author(s):  
Michael Gallagher ◽  
Jong-Uk Kim ◽  
Eric Huenger ◽  
Kai Zoschke ◽  
Christina Lopper ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Flip Chip ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Curing Temperature ◽  
Wafer Level ◽  
Mechanical Adhesion ◽  
3D Stacking ◽  
Dry Etch

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Study on the Glass Silicon Anodic Direct Bonding Parameters

2016 ◽  
Vol 1 (1) ◽  
pp. 71
Author(s):  
Li Jia ◽  
Guo Hao ◽  
Guo Zhiping ◽  
Miao Shujing ◽  
Wang Jingxiang
Keyword(s):  
Experimental Study ◽  
Wafer Bonding ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Bonding Time ◽  
Experimental Results ◽  
Bonding Quality ◽  
Mems Packaging ◽  
Bonding Parameters ◽  
Test Platform

<p>By MEMS packaging test platform for bonding process of bonding temperature and bonding time, and test silicon specifications experimental study. Experimental results indicate that when the bonding voltage of 1200V, bonding temperature of 445<sup>0</sup>C to 455<sup>0</sup>C, bonding time is 60s,the void fraction is less than 5%.Glass and silicon wafer bonding quality can achieve the best. The experimental results in order to improve the glass silicon bonding quality provide the basis.</p>

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