200. mm Silicon Wafer-to-Wafer Bonding with Thin Ti Layer under BEOL-Compatible Process Conditions

2004 ◽  
Vol 843 ◽  
Author(s):  
J. Yu ◽  
J. J. McMahon ◽  
J.-Q. Lu ◽  
R. J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Complete Removal ◽  
External Pressure ◽  
Reduced Form ◽  
Process Conditions ◽  
Manufacturing Cost ◽  
Wafer Level ◽  
Integrity Test ◽  
Wafer Pair

ABSTRACTWafer level monolithic three-dimensional (3D) integration is an emerging technology to realize enhanced performance and functionality with reduced form-factor and manufacturing cost. The cornerstone for this 3D processing technology is full-wafer bonding under back-end-of-the-line (BEOL) compatible process conditions. For the first time to our knowledge, we demonstrate nearly void-free 200 mm wafer-to-wafer bonding with an ultra-thin Ti adhesive coating, annealed at BEOL-compatible temperature (400 °C) in vacuum with external pressure applied. Mechanical integrity test showed that bonded wafer pair survived after a stringent three-step thinning process (grinding/polishing/wet-etching) with complete removal of top Si wafer, while allowing optical inspection of bonding interface. Mechanisms contributing to the strong bonding at Ti/Si interface are briefly discussed.

Effects of Bonding Process Parameters on Wafer-to-Wafer Alignment Accuracy in Benzocyclobutene (BCB) Dielectric Wafer Bonding

2005 ◽  
Vol 863 ◽  
Author(s):  
F. Niklaus ◽  
R.J. Kumar ◽  
J.J. McMahon ◽  
J. Yu ◽  
T. Matthias ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Layer Thickness ◽  
Wafer Bonding ◽  
Three Dimensional ◽  
Bonding Process ◽  
Alignment Accuracy ◽  
Wafer Level ◽  
Bonding Parameters ◽  
Wafer Pair ◽  
The Impact

AbstractWafer-level three-dimensional (3D) integration is an emerging technology to increase the performance and functionality of integrated circuits (ICs). Aligned wafer-to-wafer bonding with dielectric polymer layers (e.g., benzocyclobutene (BCB)) is a promising approach for manufacturing of 3D ICs, with minimum bonding impact on the wafer-to-wafer alignment accuracy essential. In this paper we investigate the effects of thermal and mechanical bonding parameters on the achievable post-bonding wafer-to-wafer alignment accuracy for polymer wafer bonding with 200 mm diameter wafers. Our baseline wafer bonding process with softbaked BCB (∼35% cross-linked) has been modified to use partially cured (∼ 43% crosslinked) BCB. The partially cured BCB layer does not reflow during bonding, minimizing the impact of inhomogeneities in BCB reflow under compression and/or slight shear forces at the bonding interface. As a result, the non-uniformity of the BCB layer thickness after wafer bonding is less than 0.5% of the nominal layer thickness and the wafer shift relative to each other during the wafer bonding process is less than 1 μm (average) for 200 mm diameter wafers. The critical adhesion energy of a bonded wafer pair with the partially cured BCB wafer bonding process is similar to that with soft-baked BCB.

Upscaling panel size for Cu plating on FOPLP (Fan Out Panel Level Packaging) applications to reduce manufacturing cost

2018 ◽  
Vol 2018 (1) ◽  
pp. 000037-000042
Author(s):  
Henning Hübner ◽  
Christian Ohde ◽  
Dirk Ruess
Keyword(s):  
Large Scale ◽  
Metal Deposition ◽  
Process Conditions ◽  
Manufacturing Cost ◽  
Wafer Level ◽  
Process Technology ◽  
Process Step ◽  
Glass Substrates ◽  
Component Design ◽  
Advanced Packaging

Abstract Electrolytic metal deposition is a key process step in the manufacturing of vertical and horizontal interconnections used in today's PCBs and IC substrates on one hand and advanced packaging applications on the other hand. Historically both application areas were clearly defined and separated by different requirements in feature sizes and substrate formats. PCBs and IC substrates were based on organic large scale substrates with rather large features while advanced packaging technology is wafer based with the capability to incorporate fine features down to a few microns. The ever increasing demand of higher performance, lower cost and thinner end user devices like smartphones require intense developments and innovation in all areas of the electronic component design including the substrate and chip packaging. Latest manufacturing technologies in both areas like fan-out wafer level packaging and advanced substrates are constantly emerging and promise to be a critical piece to meet these requirements. As a consequence both areas are currently merging while creating a new application segment. This segment combines the request of small feature sizes with the manufacturability on large scale substrates. Obviously many of the traditional process technologies like plating and available equipment cannot be easily adopted and need certain developments, adaptions and improvements. In this respect, a key challenge in the area of electrolytic metal deposition is the combination of various challenging requirements: creation of feature sizes down to 2μm L/S with heterogeneous feature density on large substrates up to 600mm at excellent metal thickness uniformity and high plating speed. The paper presents latest studies and conclusions in critical performance areas of the plating process such as electrolyte fluid dynamics, impact of anode design, pulse reverse rectification and newly designed electrolytes. Finally latest test results of optimized process conditions will be discussed in detail with different feature sizes providing data of within die and within substrate uniformity. All tests are done on panel level, both organic and glass substrates. The latest findings and achievements of the discussed panel based plating process technology will support the industry to develop panel based packaging processes that meet both technical and commercial requirements.

scholarly journals Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1586
Author(s):  
Zhong Fang ◽  
Peng You ◽  
Yijie Jia ◽  
Xuchao Pan ◽  
Yunlei Shi ◽  
...  
Keyword(s):  
Adhesive Bonding ◽  
Low Cost ◽  
Three Dimensional ◽  
System Level ◽  
Process Conditions ◽  
Wafer Level ◽  
3D Integration ◽  
Bonding Pressure ◽  
Curing Conditions ◽  
Integration Technology

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

Advanced Anodic Bonding Processes For MEMS Applications

2003 ◽  
Vol 782 ◽  
Author(s):  
V. Dragoi ◽  
P. Lindner ◽  
T. Glinsner ◽  
M. Wimplinger ◽  
S. Farrens
Keyword(s):  
Three Dimensional ◽  
Anodic Bonding ◽  
Process Conditions ◽  
Wafer Level ◽  
Process Step ◽  
Packaging Process ◽  
Powerful Technique ◽  
Wafer Level Packaging ◽  
Single Process ◽  
Single Process Step

ABSTRACTAnodic bonding is a powerful technique used in MEMS manufacturing. This process is applied mainly for building three-dimensional structures for microfluidic applications or for wafer level packaging. Process conditions will be evaluated in present paper. An experimental solution for bonding three wafers in one single process step (“triple-stack bonding”) will be introduced.

Mechanisms of Low-Temperature Ti/Si-Based Wafer Bonding

2005 ◽  
Vol 863 ◽  
Author(s):  
Jian Yu ◽  
Yinmin Wang ◽  
Arthur W. Haberl ◽  
Hassa Bakhru ◽  
Jian-Qiang Lu ◽  
...  
Keyword(s):  
Silicon Wafer ◽  
Wafer Bonding ◽  
Rutherford Backscattering Spectrometry ◽  
Three Dimensional ◽  
Amorphous Layer ◽  
Bonding Interface ◽  
Native Oxide ◽  
Wafer Level ◽  
Transmission Electron ◽  
Strong Adhesion

AbstractThree-dimensional (3D) wafer-level integration is receiving increased attention with various wafer bonding approaches being evaluated. Recently, we explored an alternative lowtemperature Ti/Si-based wafer bonding, in which an oxidized silicon wafer was successfully bonded with a prime silicon wafer at 400°C using 30 nm sputtered Ti as adhesive. The bonded pairs show excellent bonding uniformity and mechanical integrity. Rutherford backscattering spectrometry (RBS) was applied to confirm the interdiffusion occurred in the interlayer. The bonding interface was examined by high-resolution transmission electron microscopy (HRTEM) assisted with electron energy loss spectroscopy (EELS) elemental mapping and energy dispersive X-ray spectroscopy (EDX). Characterization of the bonding interface indicates the strong adhesion achieved is attributed to an amorphous layer formed by interdiffusion of Si and oxygen into Ti interlayer and the unique ability to reduce native oxide (SiO2) by Ti even at low temperatures.

Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

2004 ◽  
Vol 816 ◽  
Author(s):  
J.-Q. Lu ◽  
G. Rajagopalan ◽  
M. Gupta ◽  
T.S. Cale ◽  
R.J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
3D Integration ◽  
Edge Chipping ◽  
3D Ics ◽  
Process Compatibility ◽  
Wafer Thinning ◽  
Thinning Process

AbstractMonolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu/Dielectric Wafer-to-Wafer Bonding

2017 ◽  
Vol 139 (1) ◽  
Author(s):  
Herman Oprins ◽  
Vladimir Cherman ◽  
Tomas Webers ◽  
Abdellah Salahouelhadj ◽  
Soon-Wook Kim ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
Wafer Bonding ◽  
Three Dimensional ◽  
Measurement Data ◽  
Thermal Characterization ◽  
Test Chip ◽  
Thermal Test ◽  
Wafer Pair ◽  
Transient Measurement

In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of line (BEOL) for the experimental thermal characterization of the intertier thermal resistance of wafer-pairs fabricated by three-dimensional (3D) hybrid Cu/dielectric wafer-to-wafer (W2W) bonding. The thermal test structures include heater elements and temperature sensors. The steady-state or transient measurement data are combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die–die interface created by hybrid wafer-to-wafer bonding is compared to literature data for die-to-die (D2D) or die-to-wafer (D2W) stacking with microbumps. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing

2016 ◽  
Vol 75 (9) ◽  
pp. 345-353 ◽  
Author(s):  
F. Kurz ◽  
T. Plach ◽  
J. Suss ◽  
T. Wagenleitner ◽  
D. Zinner ◽  
...  
Keyword(s):  
Low Temperature ◽  
High Precision ◽  
Wafer Bonding ◽  
Wafer Level ◽  
3D Ics ◽  
Direct Wafer Bonding ◽  
Bonding Technology
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