scholarly journals MFMIS Negative Capacitance FinFET Design for Improving Drive Current

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1423
Author(s):  
Jinhong Min ◽  
Changhwan Shin
Keyword(s):  
Gate Voltage ◽  
Computer Aided Design ◽  
Parasitic Capacitance ◽  
Negative Capacitance ◽  
Gate Leakage Current ◽  
Drive Current ◽  
Aided Design ◽  
Voltage Degradation ◽  
Coercive Electric Field ◽  
Threshold Voltage Degradation

The effect of remnant polarization (Pr), coercive electric-field (Ec), and parasitic capacitance of baseline device on the drive current (ION) of a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) negative capacitance FinFET (NC FinFET) was investigated. The internal gate voltage in the MFMIS structure was simulated considering gate leakage current. Using technology computer aided design (TCAD) tool, the device characteristic of 7 nm FinFET was quantitatively estimated, for the purpose of modeling the baseline device of MFMIS NC FinFET. The need for appropriate parasitic capacitance to avoid performance degradation in MFMIS NC FinFET was presented through the internal gate voltage estimation. With an appropriate parasitic capacitance, the effect of Pr and Ec was investigated. In the case of Ec engineering, it is inappropriate to improve the device performance for MFMIS NC FinFET without threshold voltage degradation. Rather than Ec engineering, an adequate Pr value for achieving high ION in MFMIS NC FinFET is suggested.

scholarly journals Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1585
Author(s):  
Hanbin Wang ◽  
Jinshun Bi ◽  
Mengxin Liu ◽  
Tingting Han
Keyword(s):  
Gate Voltage ◽  
Computer Aided Design ◽  
Silicon On Insulator ◽  
Fully Depleted ◽  
Gate Structure ◽  
Different Temperatures ◽  
Dual Gate ◽  
Sensitivity Changes ◽  
Increasing Temperature ◽  
Aided Design

This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.

scholarly journals LoGHeD: An effective approach for negative differential resistance effect suppression in negative capacitance transistors

2022 ◽  
Author(s):  
Ziqiang Xie ◽  
Weifeng Lyu ◽  
Mengxue Guo ◽  
Mengjie Zhao
Keyword(s):  
Negative Differential Resistance ◽  
Computer Aided Design ◽  
Differential Resistance ◽  
Silicon On Insulator ◽  
Negative Capacitance ◽  
Fully Depleted ◽  
In Doping ◽  
Drain Side ◽  
Negative Differential Resistance Effect ◽  
Aided Design

Abstract A negative capacitance transistor (NCFET) with fully depleted silicon-on-insulator (FDSOI) technology (NC-FDSOI) is one of the promising candidates for next-generation low-power devices. However, it suffers from the inherent negative differential resistance (NDR) effect, which is very detrimental to device and circuit designs. Aiming at overcoming this shortcoming, this paper proposes for the first time to use local Gaussian heavy doping technology (LoGHeD) in the channel near the drain side to suppress the NDR effect in the NC-FDSOI. The technical computer-aided design (TCAD) simulation results have validated that the output conductance (GDS) with LoGHeD, which is used to measure the NDR effect, increases compared to the conventional NC-FDSOI counterpart and approaches zero. With the increase in doping concentration, the inhibitory capability of the NDR effect shows a monotonously increasing trend. In addition, the proposed approach maintains and even enhances performances of the NC-FDSOI transistor regarding the electrical parameters, such as threshold voltage (VTH), sub-threshold swing (SS), switching current ratio (ION/IOFF), and drain-induced barrier lowering (DIBL).

scholarly journals Effects of Back-Gate Bias on Subthreshold Swing of Tunnel Field-Effect Transistor

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1415 ◽  
Author(s):  
Jaehong Lee ◽  
Garam Kim ◽  
Sangwan Kim
Keyword(s):  
Gate Voltage ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Subthreshold Swing ◽  
Gate Bias ◽  
Back Gate ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

In this study, the effects of back-gate bias on the subthreshold swing (S) of a tunnel field-effect transistor (TFET) were discussed. The electrostatic characteristics of the back-gated TFET were obtained using technology computer-aided design (TCAD) simulation and were explained using the concepts of turn-on and inversion voltages. As a result, S decreased, when the back-gate voltage increased; this behavior is attributed to the resultant increase in inversion voltage. In addition, it was found that the on–off current ratio of the TFET increased with a decrease in S due to the back-gate voltage.

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