Burn-in Failure Analysis of 0.5μm 1MB SRAM: Barrier Glue Layer Cracks and Tungsten Plug “Worm Holes”

1996 ◽  
Author(s):  
E. Widener ◽  
S. Tatti ◽  
P. Schani ◽  
S. Crown ◽  
B. Dunnigan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Product Quality ◽  
Cmos Process ◽  
Designed Experiments ◽  
Root Cause ◽  
Poly Silicon ◽  
New Process ◽  
Supply Current ◽  
Electrical Analysis ◽  
Current Characteristics

Abstract A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

scholarly journals Identification of Yield Limiting Defects in a 0.5 Micron, Shallow Trench Isolation Technology

1999 ◽  
Author(s):  
Christopher L. Henderson ◽  
Charles E. Hembree ◽  
Jerry M. Soden ◽  
Thomas J. Headley ◽  
Bruce L. Draper
Keyword(s):  
Power Supply ◽  
Random Access ◽  
Shallow Trench Isolation ◽  
Root Cause ◽  
Trench Isolation ◽  
Static Random Access Memories ◽  
Cause Of Failure ◽  
Radiation Hardened ◽  
Supply Current ◽  
Electrical Analysis

Abstract During the development and qualification of a radiation-hardened, 0.5 μm shallow trench isolation technology, several yield-limiting defects were observed. The 256K (32K x 8) static-random access memories (SRAMs) used as a technology characterization vehicle had elevated power supply current during wafer probe testing. Many of the die sites were functional, but exhibited quiescent power supply current (IDDQ) in excess of 100 μA, the present limit for this particular SRAM. Initial electrical analysis indicated that many of the die sites exhibited unstable IDDQ that fluctuated rapidly. We refer to this condition as “jitter.” The IDDQ jitter appeared to be independent of temperature and predominately associated with the larger 256K SRAMs and not as prevalent in the 16K SRAMs (on the same reticle set). The root cause of failure was found to be two major processing problems: salicide bridging and stress-induced dislocations in the silicon island

CMOS Backside Deprocessing With TMAH / IPA as a Sample Preparation Procedure for Failure Analysis

2002 ◽  
Author(s):  
Seth Prejean ◽  
Victoria Bruce ◽  
Joyce Burke
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Process Development ◽  
Future Research ◽  
Cmos Process ◽  
Preparation Technique ◽  
Root Cause ◽  
Sample Preparation Procedure ◽  
Root Cause Failure Analysis ◽  
Preparation Techniques

Abstract This paper is about a sample preparation technique that is based on a previous research publication1. The technique was initially used for the investigation of salicide formation for CMOS process development. The initial results were very good and proved to be helpful with root cause failure analysis. Once the technique proved to be a viable failure analysis (FA) tool, a research team was formed to continue the development. This paper is written in conjunction with this team. The team is presently focused on developing a repeatable and reliable methodology of deprocessing CMOS devices from the backside. The team is also developing a methodology for post deprocessing analysis once the backside silicon is removed. The research that is presented here focuses on packaged as well as unpackaged devices. Etch rates and selectivity of tetramethylammoniumhydroxide (TMAH) is investigated along with temperature dependencies. Package material and chemical interference issues were discovered and remedied with special preparation techniques. Post deprocessing analysis is considered and many ideas are proposed as part of future research.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Analysis Approach on DMOS Transistor Vth Mismatch Due to Trapped Charges

2015 ◽  
Author(s):  
Hashim Ismail ◽  
Ang Chung Keow ◽  
Kenny Gan Chye Siong
Keyword(s):  
Failure Analysis ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Analysis Approach ◽  
Test Results ◽  
Root Cause ◽  
Switching Event ◽  
Output Transistor ◽  
Event Based ◽  
Trapped Charge

Abstract An output switching malfunction was reported on a bridge driver IC. The electrical verification testing revealed evidence of an earlier over current condition resulting from an abnormal voltage sense during a switching event. Based on these test results, we developed the hypothesis that a threshold voltage mismatch existed between the sense transistor and the output transistor. This paper describes the failure analysis approach we used to characterize the threshold voltage mismatch as well as our approach to determine the root cause, which was trapped charge on the gate oxide of the sense transistor.

Failure Analysis of Single Shared Column Fail in DRAM Using Nano-Probing Technique

2008 ◽  
Author(s):  
Suk Min Kim ◽  
Jung Ho Lee ◽  
Jong Hak Lee ◽  
Hyung Ki Kim ◽  
Myung Sick Chang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Electrical Characteristics ◽  
The Future ◽  
Electrical Analysis

Abstract We report an analysis of a single shared column fail on DRAM technology using a nano-probing technique in this work. The electrical characteristics of the failed transistors show that the column fails were caused by two different failure mechanisms: abnormal contact and implant profiles. We believe that electrical analysis using nano-probing will be a powerful tool for non-visible failure analysis in the future because it is impossible to clearly reveal these two different failure mechanisms solely using physical failure methods.

Root Cause Analyses of Metal Bridging for Copper Damascene Process

2005 ◽  
Author(s):  
Z. G. Song ◽  
S. P. Neo ◽  
S. K. Loh ◽  
C. K. Oh
Keyword(s):  
Failure Mechanisms ◽  
Copper Corrosion ◽  
Microelectronic Device ◽  
Root Cause ◽  
Damascene Process ◽  
New Process ◽  
Copper Cmp

Abstract New process will introduce new failure mechanisms during microelectronic device manufacturing. Even if the same defect, its root causes can be different for different processes. For aluminum(Al)-tungsten(W) metallization, the root cause of metal bridging is quite simple and mostly it is blocked etch or under-etch. But, for copper damascene process, the root causes of metal bridging are complicated. This paper has discussed the various root causes of metal bridging for copper damascene process, such as those related to litho-etch issue, copper CMP issue, copper corrosion issue and so on.

A New Deprocess Flow of Failure Analysis for MEMS Motion Sensor

2013 ◽  
Author(s):  
Chun-An Huang ◽  
Han-Yun Long ◽  
King-Ting Chiang ◽  
Li Chuang ◽  
Kevin Tsui
Keyword(s):  
Failure Analysis ◽  
Optical Microscopy ◽  
Motion Sensor ◽  
Thermal System ◽  
Layer By Layer ◽  
Sensor Failure ◽  
Process Flow ◽  
New Process ◽  
Cutting System ◽  
Successful Observation

Abstract This paper demonstrates a new de-process flow for MEMS motion sensor failure analysis, using layer by layer deprocessing to locate defect points. Analysis tools used in this new process flow include IR optical microscopy, thermal system, SEM and a cutting system to de-process of MEMS motion sensor and successful observation defect points.

Precision Xe Plasma FIB Delayering for Physical Failure Analysis of Sub-20 nm Microprocessor Devices

2017 ◽  
Author(s):  
D. Zudhistira ◽  
V. Viswanathan ◽  
V. Narang ◽  
J.M. Chin ◽  
S. Sharang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Dielectric Films ◽  
Planar Surface ◽  
Chemical Methods ◽  
Root Cause ◽  
Essential Step ◽  
Dielectric Layers ◽  
Wet Chemical ◽  
20 Nm ◽  
Low K

Abstract Deprocessing is an essential step in the physical failure analysis of ICs. Typically, this is accomplished by techniques such as wet chemical methods, RIE, and mechanical manual polishing. Manual polishing suffers from highly non-uniform delayering particularly for sub 20nm technologies due to aggressive back-end-of-line scaling and porous ultra low-k dielectric films. Recently gas assisted Xe plasma FIB has demonstrated uniform delayering of the metal and dielectric layers, achieving a planar surface of heterogeneous materials. In this paper, the successful application of this technique to delayer sub-20 nm microprocessor chips with real defects to root cause the failure is presented.

SEM-Based Nanoprobing on 40, 32 and 28 nm CMOS Devices Challenges for Semiconductor Failure Analysis

2013 ◽  
Author(s):  
Erik Paul ◽  
Holger Herzog ◽  
Sören Jansen ◽  
Christian Hobert ◽  
Eckhard Langer
Keyword(s):  
Electron Microscope ◽  
High Resolution ◽  
Scanning Electron Microscope ◽  
Failure Analysis ◽  
Case Studies ◽  
State Of The Art ◽  
Root Cause ◽  
Highly Efficient ◽  
Technology Nodes ◽  
Scanning Electron

Abstract This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.

Marginal RF Gain Investigation and Root Cause Determination

2013 ◽  
Author(s):  
Keith Harber ◽  
Steve Brockett
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Power Amplifier ◽  
Physical Analysis ◽  
Root Cause ◽  
S Parameter ◽  
Mode Of Operation ◽  
S Parameters

Abstract This paper outlines the failure analysis of a Radio Frequency only (RF-only) failure on a complex Multimode Multiband Power Amplifier (MMPA) module, where slightly lower gain was observed in one mode of operation. 2 port S-parameter information was collected and utilized to help localize the circuitry causing the issue. A slight DC electrical difference was observed, and simulation was utilized to confirm that difference was causing the observed S-parameters. Physical analysis uncovered a very visible cause for the RF-only failure.

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