Reversible Barrel Shifter and Shift Register

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

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Linear feedback shift register and integer theory: a state-of-art approach in security issues over e-commerce

Electronic Commerce Research ◽

10.1007/s10660-021-09477-w ◽

2021 ◽

Author(s):

Anirban Bhowmik ◽

Sunil Karforma

Keyword(s):

Shift Register ◽

Linear Feedback Shift Register ◽

Linear Feedback ◽

Security Issues ◽

Feedback Shift Register ◽

State Of Art

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A Novel Cross-Latch Shift Register Scheme for Low Power Applications

Applied Sciences ◽

10.3390/app11010129 ◽

2020 ◽

Vol 11 (1) ◽

pp. 129

Author(s):

Po-Yu Kuo ◽

Ming-Hwa Sheu ◽

Chang-Ming Tsai ◽

Ming-Yan Tsai ◽

Jin-Fa Lin

Keyword(s):

Power Consumption ◽

Supply Voltage ◽

Electrical Power ◽

Average Power ◽

Leakage Power ◽

Shift Register ◽

Cmos Process ◽

Average Power Consumption ◽

Simulation Results ◽

Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

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