Dual-Threshold CMOS for Complementary Pass-Transistor Adiabatic Logic with Gate-Length Biasing Techniques
Gate-Length Biasing Technique of Complementary Pass-Transistor Adiabatic Logic for Leakage Reduction
2010 ◽
Vol 159
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pp. 180-185
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2012 ◽
Vol 4
(12)
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pp. 98-106
2013 ◽
Vol 7
(5)
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pp. 1260-1268
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2013 ◽
Vol 6
(3)
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pp. 173-182
Keyword(s):
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2010 ◽
Vol 39
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pp. 73-78
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1997 ◽
Vol 44
(10)
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pp. 842-846
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