Gate-Length Biasing Technique of Complementary Pass-Transistor Adiabatic Logic for Leakage Reduction

2010 ◽  
Vol 159 ◽  
pp. 180-185 ◽  
Author(s):  
Jian Ping Hu ◽  
Yu Zhang
Keyword(s):  
Energy Savings ◽  
Cmos Process ◽  
Gate Length ◽  
Mos Transistors ◽  
Traffic Light ◽  
Leakage Currents ◽  
Two Phase ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
The One

Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. To decrease leakage power dissipations is becoming more and more important in low-power nanometer circuits. This paper proposes a gate-length biasing technique for complementary pass-transistor adiabatic logic (CPAL) circuits to reduce sub-threshold leakage dissipations. The flip-flops based on CPAL circuits with gate-length biasing techniques are presented. A traffic light controller using two-phase CPAL with gate-length biasing technique is demonstrated at 45nm CMOS process. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE. Simulation results show that the CPAL traffic light controller with the gate-length biasing technique attains 20% to 5% energy savings compared with the one using the original gate length 25MHz to 200MHz.

Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration

2010 ◽  
Vol 39 ◽  
pp. 73-78 ◽  
Author(s):  
Jin Tao Jiang ◽  
Li Fang Ye ◽  
Jian Ping Hu
Keyword(s):  
Gate Oxide ◽  
Cmos Process ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Leakage Reduction ◽  
Nanometer Cmos ◽  
Benchmark Circuit ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Cmos Processes

Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

An Improved CAL Register File with Dual-Threshold Technique for Leakage Reduction

2010 ◽  
Vol 159 ◽  
pp. 186-191 ◽  
Author(s):  
Jian Ping Hu ◽  
Jia Guo Zhu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Total Power ◽  
Cmos Process ◽  
Register File ◽  
Mos Transistors ◽  
Leakage Currents ◽  
Micro Power ◽  
Scaling Down ◽  
Threshold Technique

Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. The leakage dissipation caused by leakage currents is becoming an increasingly important fraction of the total power dissipation in nanometer integrated circuits. To decrease leakage power dissipations is becoming more and more important in micro-power nanometer circuits. An improved CAL register file using DTCMOS (Dual-Threshold Technique) for reducing leakage dissipations in active mode is addressed in this paper. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE at 45nm CMOS process. Simulation results show that the register file with dual-threshold can reduce about 15.6% power dissipations.

Leakage Power Estimation of Adiabatic Circuits Using SPICE in Nanometer CMOS Processes

2010 ◽  
Vol 108-111 ◽  
pp. 625-630 ◽  
Author(s):  
Yang Bo Wu ◽  
Jian Ping Hu ◽  
Hong Li
Keyword(s):  
Significant Proportion ◽  
Power Estimation ◽  
Low Power Design ◽  
Leakage Power ◽  
Cmos Process ◽  
Cmos Circuits ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
Total Leakage ◽  
Pass Transistor

In deep sub-micro CMOS process, the leakage power is becoming a significant proportion in power dissipation. Hence, estimating the leakage power of CMOS circuits is very important in low-power design. In this paper, an estimation technology for the total leakage power of adiabatic logic circuits by using SPICE is proposed. The basic principle of power estimation for traditional CMOS circuits using SPICE is introduced. According to the energy dissipation characteristic of adiabatic circuits, the estimation technology for leakage power is discussed. Taken as an example, the estimation for total leakage power dissipations of PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits is illustrated using the proposed estimation technology.

LOW POWER ENERGY RECOVERY COMPLEMENTARY PASS-TRANSISTOR LOGIC

2006 ◽  
Vol 15 (04) ◽  
pp. 491-504
Author(s):  
ROBERT C. CHANG ◽  
PO-CHUNG HUNG ◽  
HSIN-LEI LIN
Keyword(s):  
Energy Recovery ◽  
Power Saving ◽  
Cmos Technology ◽  
Power Reduction ◽  
Two Phase ◽  
Look Ahead ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Pass Transistor Logic ◽  
Efficient Power

A proposed adiabatic logic called Energy Recovery Complementary Pass-transistor Logic (ERCPL) is presented in this paper. It operates with a two-phase nonoverlapping power-clock supply. It uses bootstrapping to achieve efficient power saving and eliminates any nonadiabatic losses on the charge-steering devices. A scheme is used to recover part of the energy trapped in the bootstrapping nodes. We compare the energy dissipation between ERCPL and other logic circuits by simulation. Simulation results show that a pipelined ERCPL carry look-ahead adder can achieve a power reduction of 80% over the conventional CMOS case. Operation of an 8-bit ERCPL CLA fabricated using the TSMC 0.35 μm 1P4M CMOS technology has been experimentally verified.

scholarly journals Gate Leakage Reduction by Clocked Power Supply of Adiabatic Logic Circuits

2005 ◽  
Vol 3 ◽  
pp. 281-285 ◽  
Author(s):  
Ph. Teichmann ◽  
J. Fischer ◽  
E. Amirante ◽  
St. Henzler ◽  
A. Bargagli-Stoffi ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Power Supply ◽  
New Technologies ◽  
Clock Cycle ◽  
Cmos Process ◽  
Gate Leakage ◽  
Clock Period ◽  
Leakage Currents ◽  
Additional Energy ◽  
Adiabatic Logic

Abstract. Losses due to gate-leakage-currents become more dominant in new technologies as gate leakage currents increase exponentially with decreasing gate oxide thickness. The most promising Adiabatic Logic (AL) families use a clocked power supply with four states. Hence, the full VDD voltage drops over an AL gate only for a quarter of the clock cycle, causing a full gate leakage only for a quarter of the clock period. The rising and falling ramps of the clocked power supply lead to an additional energy consumption by gate leakage. This energy is smaller than the fraction caused by the constant VDD drop, because the gate leakage exponentially depends on the voltage across the oxide. To obtain smaller energy consumption, Improved Adiabatic Logic (IAL) has been introduced. IAL swaps all n- and p-channel transistors. The logic blocks are built of p-channel devices which show gate tunneling currents significantly smaller than in n-channel devices. Using IAL instead of conventional AL allows an additional reduction of the energy consumption caused by gate leakage. Simulations based on a 90nm CMOS process show a lowering in gate leakage energy consumption for AL by a factor of 1.5 compared to static CMOS. For IAL the factor is up to 4. The achievable reduction varies depending on the considered AL family and the complexity of the gate.

scholarly journals A Study on the Variable Inductor Design by Switching the Main Paths and the Coupling Coils

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1856
Author(s):  
Yen-Chung Chiang ◽  
Juo-Chen Chen ◽  
Yu-Hsin Chang
Keyword(s):  
Design Method ◽  
The Other ◽  
Cmos Process ◽  
Mos Transistors ◽  
Quality Factors ◽  
Process Technology ◽  
Variation Versus ◽  
Variable Inductor ◽  
Metal Layers ◽  
Coupled Coils

In a radio frequency (RF) system, it is possible to use variable inductors for providing tunable or selective frequency range. Variable inductors can be implemented by the microelectromechanical system (MEMS) process or by using transistors as switches to change the routing of coils or coupling quantities. In this paper, we investigated the design method of a variable inductor by using MOS transistors to switch the main coil paths and the secondary coupled coils. We observed the effects of different metal layers, turn numbers, and layout arrangements for secondary-coupled coils and compared their characteristics on the inductances and quality factors. We implemented two chips in the 0.18 m CMOS process technology for each kind of arrangement for verification. One inductor can achieve inductance values from about 300 pH to 550 pH, and the other is between 300 pH and 575 pH, corresponding to 59.3% and 62.5%, respectively, inductance variation range at 4 GHz frequency. Additionally, their fine step sizes of the switched inductances are from 0.5% to 6% for one design, and 1% to 12.5% for the other. We found that both designs achieved a large inductance tuning range and moderate inductance step sizes with a slight difference behavior on the inductance variation versus frequency.

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