Simple Methods to Measure the Additive Error and Integral Nonlinearity of Precision Thermometric Bridges

2015 ◽  
pp. 157-170 ◽  
Author(s):  
Aleksander A. Mikhal ◽  
Zygmunt L. Warsza
Keyword(s):  
Additive Error ◽  
Integral Nonlinearity

DETECTING AND CORRECTING BYTE ERRORS IN DIGITAL DATA TRANSMISSION SYSTEMS

2021 ◽  
Author(s):  
А.А. ПАВЛОВ ◽  
Ю.А. РОМАНЕНКО ◽  
А.Н. ЦАРЬКОВ ◽  
А.Ю. РОМАНЕНКО ◽  
А.А. МИХЕЕВ
Keyword(s):  
Data Transmission ◽  
Digital Data ◽  
Transmission Systems ◽  
Error Vector ◽  
Time Costs ◽  
Additive Error ◽  
Syndrome Decoding ◽  
Hardware Costs

Обоснована необходимость разработки методического аппарата, связанного с построением кода, корректирующего ошибки в заданном числе байтов информации с алгебраическим синдромным декодированием и оценкой аппаратурных и временных затрат, связанных с этой целью. Представлены правила построения корректирующего кода, исправляющего ошибки в заданном числе байтов информации, реализующего линейную процедуру построения корректирующего кода с синдромным декодированием и использованием аддитивного вектора ошибок, что позволило сократить аппаратурные затраты на построение декодирующего устройства (сократить объем памяти для хранения значений векторов ошибок). Получены выражения для оценки аппаратурных затрат на кодирование и декодирование информации при использовании предлагаемого метода коррекции пакетных ошибок. The necessity of developing a methodological apparatus related to the construction of a code that corrects errors in a given number of bytes of information with algebraic syndrome decoding and the estimation of hardware and time costs associated with this purpose is justified. The rules for constructing a correction code that corrects errors in a given number of bytes of information, implementing a linear procedure for constructing a correction code with syndrome decoding and using an additive error vector, are presented. This method made it possible to reduce the hardware costs for constructing a decoding device (reducing the amount of memory for storing the values of error vectors). Expressions are obtained for estimating the hardware costs of encoding and decoding information when using the proposed method of correcting packet errors.

scholarly journals Faster and More Accurate Measurement through Additive-Error Counters

2020 ◽  
Author(s):  
Ran Ben Basat ◽  
Gil Einziger ◽  
Michael Mitzenmacher ◽  
Shay Vargaftik
Keyword(s):  
Additive Error

scholarly journals Additive-error fine-grained quantum supremacy

Quantum ◽  
2020 ◽  
Vol 4 ◽  
pp. 329
Author(s):  
Tomoyuki Morimae ◽  
Suguru Tamaki
Keyword(s):  
Quantum Computing ◽  
Complexity Theory ◽  
Polynomial Time ◽  
Boolean Circuits ◽  
Exponential Time ◽  
Fine Grained ◽  
Additive Error ◽  
Universal Quantum ◽  
The One ◽  
Computing Models

It is known that several sub-universal quantum computing models, such as the IQP model, the Boson sampling model, the one-clean qubit model, and the random circuit model, cannot be classically simulated in polynomial time under certain conjectures in classical complexity theory. Recently, these results have been improved to ``fine-grained" versions where even exponential-time classical simulations are excluded assuming certain classical fine-grained complexity conjectures. All these fine-grained results are, however, about the hardness of strong simulations or multiplicative-error sampling. It was open whether any fine-grained quantum supremacy result can be shown for a more realistic setup, namely, additive-error sampling. In this paper, we show the additive-error fine-grained quantum supremacy (under certain complexity assumptions). As examples, we consider the IQP model, a mixture of the IQP model and log-depth Boolean circuits, and Clifford+T circuits. Similar results should hold for other sub-universal models.

scholarly journals Laser Distance Sensors Evaluation for Geomatics Researches

2020 ◽  
pp. 1831
Author(s):  
Abbas Zedan Khalaf ◽  
Bashar H Alyasery
Keyword(s):  
Reference Values ◽  
3D Modeling ◽  
Full Range ◽  
Calibration Method ◽  
Additive Error ◽  
Statistical Indicator ◽  
Laser Distance Sensor ◽  
Left And Right ◽  
Distance Sensor

In this study, an approach inspired by a standardized calibration method was used to test a laser distance meter (LDM). A laser distance sensor (LDS) was tested with respect to an LDM and then a statistical indicator explained that the former functions in a similar manner as the latter. Also, regression terms were used to estimate the additive error and scale the correction of the sensors. The specified distance was divided into several parts with percent of longest one and observed using two sensors, left and right. These sensors were evaluated by using the regression between the measured and the reference values. The results were computed using MINITAB 17 package software and excel office package. The accuracy of the results in this work was ± 4.4mm + 50.89 ppm and ± 4.96mm + 99.88 ppm for LDS1 and LDS2, respectively, depending on the LDM accuracy which was computed to the full range (100 m). Using these sensors can be very effective for industrial, 3D modeling purposes, and many other applications, especially that it is inexpensive and available in many versions.

A Low Complexity Digital Foreground Calibration Technique for CMOS Pipelined ADCs

2019 ◽  
Vol 28 (03) ◽  
pp. 1950045
Author(s):  
Maliang Liu ◽  
Sirui Zhang ◽  
Hu Jin ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Input Signal ◽  
Low Complexity ◽  
Cmos Process ◽  
Pipeline Adc ◽  
Calibration Technique ◽  
Pipelined Adcs ◽  
Integral Nonlinearity ◽  
Linear And Nonlinear ◽  
Pipeline Adcs ◽  
Foreground Calibration

A low complexity all-digital foreground calibration technique to correct linear and nonlinear errors is proposed for pipeline ADCs in this paper. This method based on the integral nonlinearity (INL) piecewise least-squares fitting improves the linearity and obtains better SNR and SFDR performance. Two switches are added to the pre-stage reference ladder to achieve an accurate measurement of the INL and DNL of the backend ADC, which reduces the calibration complexity and improves the linearity effectively. The method was applied to a 125[Formula: see text]MS/s 14-bit pipeline ADC fabricated in a 0.18[Formula: see text][Formula: see text]m CMOS process. The raw DNL and INL were 1[Formula: see text]LSB and 8[Formula: see text]LSB, respectively, without calibration, but with calibration, they were respectively improved to 0.25[Formula: see text]LSB and 2[Formula: see text]LSB. The ADC achieved an SNR of 64.5[Formula: see text]dB, an SFDR of 73.8[Formula: see text]dB and a THD of 72.7[Formula: see text]dB with a 10[Formula: see text]MHz input signal without calibration, but after calibration these figures were improved to 72.6[Formula: see text]dB, 87.5[Formula: see text]dB and 86.6[Formula: see text]dB, respectively. Its application can also be extended to SAR ADC architecture, etc.

scholarly journals Type and Cotype Constants and the Linear Stability of Wigner’s Symmetry Theorem

Symmetry ◽  
2019 ◽  
Vol 11 (9) ◽  
pp. 1107
Author(s):  
Javier Cuesta
Keyword(s):  
Banach Spaces ◽  
Linear Stability ◽  
Linear Extension ◽  
Transition Probabilities ◽  
Linear Map ◽  
Additive Error ◽  
Type And Cotype

We study the relation between almost-symmetries and the geometry of Banach spaces. We show that any almost-linear extension of a transformation that preserves transition probabilities up to an additive error admits an approximation by a linear map, and the quality of the approximation depends on the type and cotype constants of the involved spaces.

scholarly journals Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration

2018 ◽  
Vol 9 (1) ◽  
pp. 20 ◽  
Author(s):  
Yuan-Ho Chen
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Delay Lines ◽  
Differential Nonlinearity ◽  
Time Calibration ◽  
Integral Nonlinearity ◽  
Resolution Improvement ◽  
Field Programmable ◽  
Gate Array ◽  
Set Up

This paper presents a time-to-digital converter (TDC) based on a field programmable gate array (FPGA) with a tapped delay line (TDL) architecture. This converter employs dual delay lines (DDLs) to enable real-time calibrations, and the proposed DDL-TDC measures the statistical distribution of delays to permit the calibration of nonuniform delay cells in FPGA-based TDC designs. DDLs are also used to set up alternate calibrations, thus enabling environmental effects to be immediately accounted for. Experimental results revealed that relative to a conventional TDL-TDC, the proposed DDL-TDC reduced the maximum differential nonlinearity by 26% and the integral nonlinearity by 30%. A root-mean-squared value of 32 ps was measured by inputting the constant delay source into the proposed DDL-TDC. The proposed scheme also maintained excellent linearity across a range of temperatures.

scholarly journals Exploring a copula-based alternative to additive error models—for non-negative and autocorrelated time series in hydrology

2019 ◽  
Vol 575 ◽  
pp. 1031-1040 ◽  
Author(s):  
Omar Wani ◽  
Andreas Scheidegger ◽  
Francesca Cecinati ◽  
Gabriel Espadas ◽  
Jörg Rieckermann
Keyword(s):  
Time Series ◽  
Error Models ◽  
Additive Error
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