Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-Steering DACs

2021 ◽  
Author(s):  
Yang Liu ◽  
Yushen Fu ◽  
Chengyu Huang ◽  
Huazhong Yang ◽  
Xueqing Li
Keyword(s):  
Current Steering ◽  
Switching Sequence ◽  
Dynamic Switching ◽  
Integral Nonlinearity

SFDR Improvement Algorithms for Current-Steering DACs

2015 ◽  
Vol 643 ◽  
pp. 101-108 ◽  
Author(s):  
Shaiful Nizam Mohyar ◽  
Masahiro Murakami ◽  
Atsushi Motozawa ◽  
Haruo Kobayashi ◽  
Osamu Kobayashi ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Current Source ◽  
Weighted Averaging ◽  
Current Steering ◽  
Switching Sequence ◽  
Digital To Analog Converters ◽  
Compensation Methods ◽  
Spurious Free Dynamic Range ◽  
Data Weighted Averaging ◽  
Combined Algorithm

This paper presents algorithms for improving spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs) — targeted at communication applications — by minimizing both current-source mismatches and glitches. Conventional segmented current-steering DACs suffer from static mismatches among current sources which cause nonlinearity and degrade SFDR, though glitch energy is relatively small. The data-weighted averaging (DWA) algorithm can reduce static current source mismatch effects, but it increases the effects of glitch energy. Here we investigate the use of both conventional Switching-Sequence Post-Adjustment (SSPA) calibration and One–Element-Shifting (OES) methods in order to reduce the effects of both nonlinearity and glitch energy. For further improvement, we propose and investigate a fully-digital combined algorithm to reduce static current source mismatch effects with minimal increase in the glitch energy. We also did simulations of the effect of combining these two compensation methods. Our MATLAB simulations show that the combined algorithm can improve SFDR performance by 24 dB, 22dB and 2dB compared to conventional thermometer-coded, one-element-shifting and SSPA methods respectively in some conditions. When we take current mismatch into account, the combined algorithm causes glitch energy to increase by only 0.02 to 0.2 % compared to the other three methods alone.

Switching sequence optimization for gradient errors compensation in the current-steering DAC design

2020 ◽  
Vol 95 ◽  
pp. 104662 ◽  
Author(s):  
Kejun Wu ◽  
Jing Li ◽  
Xiangzhan Wang ◽  
Ning Ning ◽  
Kaikai Xu ◽  
...  
Keyword(s):  
Current Steering ◽  
Sequence Optimization ◽  
Switching Sequence ◽  
Current Steering Dac

Impact-Based Area Allocation for Yield Optimization in Integrated Circuits

2016 ◽  
Vol 1 (6) ◽  
Author(s):  
Billion Abraham ◽  
Arif Widodo ◽  
Poki Chen
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Current Steering ◽  
Yield Optimization ◽  
Digital To Analog Converter ◽  
Integral Nonlinearity ◽  
Analog Converter ◽  
Layout Area ◽  
Binary Weighted ◽  
The Impact

Abstract In analog integrated circuit (IC) layout, area allocation is a very important issue for achieving good mismatch cancellation. However, most IC layout papers focus only on layout strategy to reduce systematic mismatch. In 2006, an outstanding paper presenting area allocation strategy was published to introduce technique for random mismatch reduction. Instead of using general theoretical study to prove the strategy, this research presented close-to-optimum simulations only on case-bycase basis. The impact-based area allocation for yield optimization in integrated circuits is proposed in this chapter. To demonstrate the corresponding strategy, not only a theoretical analysis but also an integral nonlinearity-based yield simulation will be given to derive optimum area allocation for binary weighted current steering digital-to-analog converter (DAC). The result will be concluded to convince IC designers how to allocate area for critical devices in an optimum way.

A Fully Differential Variable Gain Amplifier for Portable Impedance Sensing Applications

2019 ◽  
Vol 7 ◽  
Author(s):  
Jorge Pérez Bailón ◽  
Jaime Ramírez-Angulo ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Active Area ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Current Steering ◽  
Impedance Sensing ◽  
Variable Gain ◽  
Fully Differential ◽  
Sensing Applications ◽  
Constant Bandwidth

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

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